High-density low-power-operating dram device adopting 6F/sup 2/ cell scheme with novel S-RCAT structure on 80nm feature size and beyond

Oh, Hansu; Kim, J.Y.; Park, S.G.; Kim, D.H.; Kim, S.E.; Woo, D. S.; Lee, Y.S.; Ha, Geun-Hyoung; Park, J.M.; Kang, Nam-Soo; Kim, H.J.; Hwang, Jisoo; Kim, B.Y.; Cho, Y.S.; Choi, Jung Kyu; Lee, B.H.; Cho, M.H.; Kim, Y.I.; Shin, Dongsuk; Shim, M.S.; Choi, Won-Jun; Lee, G.P.; Park, Y.J.; Lee, W.S.; Ryu, Byung-Il

doi:10.1109/essder.2005.1546614

Cited by 7 publications

(1 citation statement)

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“…A notable difference is observed in the shifting behavior of the curves; the standard device's characteristics shifted in parallel, whereas our developed device exhibited a dispersed shift, resulting in a larger threshold voltage (Vt) shift under the same current conditions. This new device effectively functions as two parallel transistors: one with a complete core triple-layer structure and another consisting only of an oxide layer on the sidewall [12,13]. During programming, the Vt of the sidewall transistor remains constant, while the Vt of the triple-layer structure transistor increases due to the introduction of the charge trap layer, leading to a non-linear shift in Vt. Our device demonstrated a decline in subthreshold swing (SS) characteristics, which was attributed to differences in structural design.…”

Section: Methodsmentioning

confidence: 99%

Engineering Improvement of the Core Layers of Charge Trapping Flash Memory Based on Doped HfO2 and Segmented Fabrication

Wang,

Lu,

Xiang

et al. 2024

Electronics

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An engineering approach was applied to modify the core layers of charge-trapping flash (CTF) memory—the blocking layer, charge-trapping layer, and tunneling layer. The doping of Ti in the charge-trapping layer and the use of Si-doped HfO2 for the tunneling layer could optimize charge capture and leakage control. This design enhances programming and erasing speeds and increases overall device stability by creating more corner fields and using the Coulomb blockade effect. Experimental results demonstrate a larger memory window and better charge retention for the new device at the same charge-trapping layer thickness. These findings signify the advancement of the new CTF memory in balancing fast programming and long-term charge retention. The long-standing contradiction between charge capturing and retention could be partially resolved by using this engineering method.

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Section: Methodsmentioning

confidence: 99%