High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices

Chiang, Meng-Hsueh; Kim, Keunwoo; Chuang, Ching-Te; Tretz, C.

doi:10.1109/ted.2006.881052

Cited by 80 publications

(44 citation statements)

References 15 publications

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“…This is of course the logic AND functionality from a single transistor, which can be employed in CMOS NAND gates as shown in Fig.15b. It provides impressive gains in Si area usage (∼50% reduction), switching speed (11% improvement for a four-input NAND) and power dissipation (10% reduction), which are experimentally confirmed (Chiang et al, 2006). While these result are impressive in themselves, the elegancy of the concept and flexibility it can provide in reconfigurable and programmable circuits are probably so far under-appreciated.…”

Section: Reconfigurable Static Dg Cmos Logicmentioning

confidence: 71%

“…Also, the clock inputs are designed using SDDG transistors in an effort to boost pre-charge and evaluation performance. Note that each pair of inputs driving the independent gates of a single nMOSFET actually carries out an AND functionality as implied by the high-V t (Chiang et al, 2006). It is therefore important to choose and control DG-MOSFET threshold accurately for this scheme to work.…”

Section: Compact Dynamic Digital Circuitsmentioning

confidence: 99%

See 1 more Smart Citation

Tunable Analog and Reconfigurable Digital Circuits with Nanoscale DG-MOSFETs

Kaya¹,

Hamed²,

Laha³

2011

Advances in Analog Circuits

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Section: Reconfigurable Static Dg Cmos Logicmentioning

confidence: 71%

Section: Compact Dynamic Digital Circuitsmentioning

confidence: 99%

Tunable Analog and Reconfigurable Digital Circuits with Nanoscale DG-MOSFETs

Kaya¹,

Hamed²,

Laha³

2011

Advances in Analog Circuits

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“…This difference is explained by the fact that in the IG mode of low-V th FinFETs, the inversion layer can be easily formed. This channel shields further gate-to-gate coupling, and hence a huge drop in threshold voltage is not seen in this mode [17]. In contrast to low-V th devices, no inversion layer can be formed in the IG mode of high-V th FinFETs.…”

Section: Characteristics Of Low and High-v Th Devicesmentioning

confidence: 99%

“…In other words, these high-V th devices must be activated iff both their gates are activated in order to be suitable for merging series transistors. Note that high-V th FinFETs cannot be realized by engineering the channel dopant concentration, like [17], because the FinFET channel should be kept undoped to avoid excessive random dopant fluctuations. In this paper, we show that high-V th IG FinFETs can be realized by careful selection of FinFET physical parameters without the use of any additional bias voltages.…”

Section: Introductionmentioning

confidence: 99%

Dual-$V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits

Rostami

Mohanram

2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper describes the electrode work-function, oxide thickness, gate-source/drain underlap, and silicon thickness optimization required to realize dual-V th independent-gate FinFETs. Optimum values for these FinFET design parameters are derived using the physics-based University of Florida SPICE model for double-gate devices, and the optimized FinFETs are simulated and validated using Sentaurus TCAD simulations. Dual-V th FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternative gates with competitive performance and reduced input capacitance in comparison to conventional FinFET gates. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than conventional CMOS gates, e.g., implementing 12 unique Boolean functions using only four transistors. Circuit designs that balance and improve the performance of the novel gates are described. The gates are designed and calibrated using the University of Florida double-gate model into conventional and enhanced technology libraries. Synthesis results for 16 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average at 2GHz, the enhanced library reduces total power and the number of fins by 36% and 37%, respectively, over a conventional library designed using shorted-gate FinFETs in 32 nm technology.

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“…Such IG FinFETs are suitable for merging series transistors. Note that high-V th FinFETs cannot be realized by engineering the channel dopant concentration, like [12], because, the FinFET channel should be kept undoped to avoid excessive random dopant fluctuations.…”

Section: Dual-v Th Independent-gate Finfetsmentioning

confidence: 99%

Novel dual-V<inf>th</inf> independent-gate FinFET circuits

Rostami¹,

Mohanram²

2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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This paper describes gate work function and oxide thickness tuning to realize novel circuits using dual-V th independent-gate FinFETs. Dual-V th FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternatives. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than conventional forms, e.g., implementing 12 unique Boolean functions using only four transistors. The gates are designed and calibrated using the University of Florida double-gate model into a technology library. Synthesis results for 14 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average, the enhanced library reduces delay, power, and area by 9%, 21%, and 27%, respectively, over a conventional library designed using FinFETs in 32nm technology.

show abstract

High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices

Cited by 80 publications

References 15 publications

Tunable Analog and Reconfigurable Digital Circuits with Nanoscale DG-MOSFETs

Tunable Analog and Reconfigurable Digital Circuits with Nanoscale DG-MOSFETs

Dual-$V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits

Novel dual-V<inf>th</inf> independent-gate FinFET circuits

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