High doped drain double-Resurf 100V P-channel MOS on SOI 0.35 ¿m BCD technology

Palumbo, V.; Venturato, M.; Gallo, Manuel Le; Pozzobon, F.; Galbiati, Marta; Contiero, C.

doi:10.1109/ispsd.2008.4538954

Cited by 11 publications

(8 citation statements)

References 2 publications

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“…However, in source-centered device, besides being immune to the adverse effect from isolation trench, back channel conduction at on-state results in a lower saturation current density and a higher breakdown voltage. Compared to former studies [4,7], the first silicon HTRB ruggedness of the investigated source-centered structure is reasonable.…”

Section: Discussionmentioning

confidence: 43%

“…HTRB results in Fig. 9 are considered reasonable [4], and can be further improved by optimizing Poffset dose and lower the electric field peak under the tips of poly silicon field and SFP [7].…”

Section: ) High Temperature Reverse-biasing (Htrb) Stressmentioning

confidence: 89%

“…P-channel MOSFETs using field oxide as gate oxide with high breakdown voltage in both off-and on-states (field HVPMOST) are widely employed in level shifters for multioutput driving circuits such as those for display panels and motor drivers [1][2][3][4]. In those applications, area-efficient device solutions are demanded either by better cost-performance or to accommodate increased power supply voltage without penalty on large layout footprint, the latter situation are envisioned in the case of plasma display panel (PDP) for higher illumination efficiency with higher supply voltage.…”

Section: Introductionmentioning

confidence: 99%

“…For HVPMOS in n-SOI layer, its breakdown voltages are not easily scaled up with drift region length because effective RESURF is inhibited by multiple depletions/biasing from handling substrate and isolation trench [4,6,7]. In this paper, taking isolation trench into account as an integral part of device structure, we comparatively investigated the impact of layout and trench on four types of field HVPMOSTs in a thick film SOI technology.…”

Section: Introductionmentioning

confidence: 99%

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High voltage SOI P-channel field MOSFET structures

Mizushima

Sumida

et al. 2009

2009 21st International Symposium on Power Semiconductor Devices &Amp; IC's

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We comparatively investigated the impact of layout and trench on four types of field oxide Pch MOSTs in a thick film SOI technology with due consideration to isolation trench. High blocking capability (∼20V per um of drift length) for both off-and on-state breakdown voltage close to 300V, along with reasonable high temperature reverse bias ruggedness, has been experimentally realized with minimum overhead area by source-centered single trench structure in which the trench sidewall grounded.

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Section: Discussionmentioning

confidence: 43%

Section: ) High Temperature Reverse-biasing (Htrb) Stressmentioning

confidence: 89%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

High voltage SOI P-channel field MOSFET structures

Mizushima

Sumida

et al. 2009

2009 21st International Symposium on Power Semiconductor Devices &Amp; IC's

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“…8. At the same R ON,sp of around 20 m ·cm 2 , the ERT pLDMOS increases the BV by 86% in comparison with the pLDMOS device in [10]. In Fig.…”

Section: A Enhanced Resurf Effect and The Bvmentioning

confidence: 83%

A RESURF-Enhanced p-Channel Trench SOI LDMOS With Ultralow Specific on-Resistance

Zhou

Luo

et al. 2014

IEEE Trans. Electron Devices

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A low specific ON-resistance (R ON,sp ) silicon-oninsulator (SOI) p-channel LDMOS (pLDMOS) with an enhanced reduced surface field (RESURF) effect and self-shielding effect of the back-gate (BG) bias is proposed and investigated. It features an oxide trench and the p-drift region surrounding the trench, which is built on the n-SOI layer. In the OFFstate, first, the extended trench gate also acts as a gate field plate; second, the p-drift and the n-SOI layer forms a folded RESURF structure. Both increase the doping dose of the p-drift and modulate electric field (E-field) distribution; third, the oxide trench not only reduces the device pitch but also enhances the E-field strength. All of them result in a low R ON,SP and a high breakdown voltage (BV) with a reduced device pitch. The free charges induced on the SOI/buried oxide (BOX) interface not only enhance the E-field strength in the BOX but also effectively shield the influence of BG bias effect in a wide range. The proposed pLDMOS achieves state-of-the-art improvement in the tradeoff between BV and R ON,SP . Compared with the p-top SOI pLDMOS, the proposed device reduces the R ON,SP by 79% at the same BV. A strong immunity to the BG bias effect is demonstrated and analyzed in detail.Index Terms-Back gate (BG), breakdown voltage (BV), p-channel LDMOS (pLDMOS), reduced surface field (RESURF), specific ON-resistance.

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Trends in Smart Power Technologies for Automotive Applications

Diazzi

2015

Lecture Notes in Mobility

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High doped drain double-Resurf 100V P-channel MOS on SOI 0.35 ¿m BCD technology

Cited by 11 publications

References 2 publications

High voltage SOI P-channel field MOSFET structures

High voltage SOI P-channel field MOSFET structures

A RESURF-Enhanced p-Channel Trench SOI LDMOS With Ultralow Specific on-Resistance

Trends in Smart Power Technologies for Automotive Applications

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