High-Efficiency E-Band Power Amplifiers and Transmitter Using Gate Capacitance Linearization in a 65-nm CMOS Process

Xi, Tianzuo; Huang, Sherry; Guo, Shita; Gui, Ping; Huang, Daren; Chakraborty, Sudipto

doi:10.1109/tcsii.2016.2563698

Cited by 32 publications

(8 citation statements)

References 7 publications

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“…Theoretically, the maximum efficiency of Class A, AB, B and C PAs are 50%, 50%-78% (0-6 dB gain drop), 78.5% (6 dB gain drop) and 78.5% (greater than 6 dB gain drop), respectively. Studies [13][14][15][16][17] have shown some common techniques to improve the efficiency of CMOS PAs. Either, for a 20 MHz narrowband at2.4 GHz, or 10 MHz narrowband at sub-1 GHz, it is still a challenge for circuit designers to boost PAE of PA, especially when avoiding balun networks and high inductances models.…”

Section: Commonly Used Techniques In Traditional Pa Architecturesmentioning

confidence: 99%

Design and optimisation of high‐efficient class‐F ULP‐PA using envelope tracking supply bias control for long‐range low power wireless local area network IEEE 802.11ah standard using 65 nm CMOS technology

Akhter

Amin

Zia

2022

IET Circuits, Devices & Syst

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This article presents the design and optimisation of a sub‐1 GHz class‐F ultra‐low power (ULP) power amplifier (PA) in 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. An envelope tracking (ET) supply biasing technique is adopted to improve the efficiency of class‐F PA. The ET consist of a pre‐amp right before the detector in order to enhance the efficiency and save adequate amount of dc power consumption. The PA consists of two cascode cells terminated as class‐F with gate‐to‐drain feedback in order to enhance linearity and limit any harmonic component from the input signal. The novel design consumes a dc power of 3.75 mW, power added efficiency of 37.1%, operating at 915–925 MHz unlicensed band and total saturated output power of 22 dBm including 14 dBm power gain at PA, which qualifies under long‐range low power wireless local area network IEEE 802.11ah standard. The inductor‐less design for ET supply bias reduces the chip layout size to 0.13 mm2 only.

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Section: Commonly Used Techniques In Traditional Pa Architecturesmentioning

confidence: 99%

Design and optimisation of high‐efficient class‐F ULP‐PA using envelope tracking supply bias control for long‐range low power wireless local area network IEEE 802.11ah standard using 65 nm CMOS technology

Akhter

Amin

Zia

2022

IET Circuits, Devices & Syst

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“…An important criterion that designers should consider when using a transformer is the amount of power delivered from the source to the load, especially in applications such as WPT [3], [25], and impedance transformation in power amplifiers [1], [2], [4], [21], [22], [29]. We can assess the efficiency of the network with regard to the power from the transducer power gain G T , which is defined as the ratio of the power delivered to load P L to the power available from source P avs [16]:…”

Section: B Impedance Matching With Two Magnetically Coupled Coilsmentioning

confidence: 99%

“…In this section, we discuss the examination of a typical onchip winding transformer (presented in Fig. 3) that is widely used for interstage matching in millimeter-wave circuits in silicon technologies [1], [2], [29]- [31]. In this study, an onchip transformer was designed in a 0.18 µm CMOS process by using an 8.625 µm thick back-end-of-line (BEOL) stack and a 300 µm thick silicon substrate.…”

Section: Verification Of the Proposed Analysis With An On-chip Tmentioning

confidence: 99%

“…At present, numerous radio frequency integrated circuit (RFIC) designs are being implemented with transformers for various purposes such as impedance matching, impedance transformation, and signal conversion between single-ended and differential signals in various frequency bands ranging from the radio frequency (RF) to terahertz regimes. Transformers are used in many applications, including power amplifiers, low-noise amplifiers, voltage-controlled oscillators, mixers, and power-combining circuits [1]- [9]. Therefore, many studies have been published on modeling and analyzing transformers, new transformer structures, and new methods for enhancing transformer efficiency [10]- [15].…”

Section: Introductionmentioning

confidence: 99%

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Theory and Design of Impedance Matching Network Utilizing a Lossy On-Chip Transformer

Trinh

Park

2019

IEEE Access

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In this paper, we present a study on a transformer-based impedance matching network. We use a simplified transformer model comprising two magnetically coupled coils, which are driven by a source and terminated by a load. The formulae of the load and the source impedance for conjugate matching of both sides of the transformer are presented, and a figure of merit is proposed for the evaluation of the power transfer efficiency of the transformer under conjugate matching conditions. Analytical expressions are provided for constructing the widely used transformer network consisting of a resistive load and a parallel tuning capacitor. To verify the proposed work, we examined various on-chip transformers implemented in 0.18 µm CMOS technology. Simulation and measurement results for a matching network synthesized using the aforementioned analytical expressions corresponded well with the result of analysis for operating frequencies up to 72% of the self-resonant frequency of the transformer. The presented results confirm that the proposed analytical formulae based on the simplified transformer model are useful for the design and optimization of transformer-based impedance matching networks in the microwave and millimeter-wave regimes.

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“…It is challenging to implement high output power ( P out ) and high power‐added efficiency (PAE) V‐band (50–75 GHz) or W‐band (75–110 GHz) power amplifiers (PAs) using CMOS process mainly due to its low supply and breakdown voltages . To increase P out , a feasible way is to combine the power of several parallel PA units using power or current combiners.…”

Section: Introductionmentioning

confidence: 99%

A wideband CMOS power amplifier for 77 GHz automobile radar and 94 GHz image radar systems

Lin

Lan

Gao

2017

Microw. Opt. Technol. Lett.

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This article reports a wideband four‐way CMOS power amplifier for 77 GHz automobile radar and 94 GHz image radar systems in 90 nm CMOS technology. The PA comprises a two‐stage common‐source (CS) cascaded input stage with wideband π‐match input, inter‐stage, and output networks, followed by a two‐way cascode gain stage using miniature zero‐degree two‐way divider and combiner, and a four‐way CS output stage using miniature zero‐degree four‐way divider and combiner. At each branch's input terminal (i.e., drain terminal of the parallel CS output stage), the miniature zero‐degree four‐way combiner can convert the serial RL load to the optimal load impedance [corresponds to the optimal output power (Pout) and power‐added efficiency (PAE)] of the output stage transistors. The PA achieves power gain of 23.9, 24.1, and 20.4 dB, respectively, at 71, 77, and 94 GHz. In addition, the PA achieves Pout of 12.3, 12.2, and 9.7 dBm, respectively, at 71, 77, and 94 GHz. The maximal PAE is 18.2%, 17.3%, and 8.9%, respectively, at 71, 77, and 94 GHz. The excellent performance of the CMOS PA indicates that it is suitable for both 77 GHz automobile radar and 94 GHz image radar transceivers.

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High-Efficiency E-Band Power Amplifiers and Transmitter Using Gate Capacitance Linearization in a 65-nm CMOS Process

Cited by 32 publications

References 7 publications

Design and optimisation of high‐efficient class‐F ULP‐PA using envelope tracking supply bias control for long‐range low power wireless local area network IEEE 802.11ah standard using 65 nm CMOS technology

Design and optimisation of high‐efficient class‐F ULP‐PA using envelope tracking supply bias control for long‐range low power wireless local area network IEEE 802.11ah standard using 65 nm CMOS technology

Theory and Design of Impedance Matching Network Utilizing a Lossy On-Chip Transformer

A wideband CMOS power amplifier for 77 GHz automobile radar and 94 GHz image radar systems

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