Silicon-based integrated photonics holds the promise of revolutionizing key technologies, such as telecommunications, computing, and lab-on-chip systems. One can achieve diverse functionalities in two ways: on the wafer surface ("on-chip") or within its bulk ("in-chip"), the latter gaining recognition due to recent advancements in laser lithography. Until recently, 3D in-chip laser writing has only been utilized for single-level devices, leaving a vast potential for monolithic and multilevel functionality within silicon untapped. In our previous research, we successfully designed and fabricated multilevel, high-efficiency diffraction gratings in silicon using nanosecond laser pulses. Their high performance stemmed from effective field enhancement at Talbot self-imaging planes. Our current work takes a theoretical approach, investigating how varying the grating period affects the performance of in-chip multilevel gratings. We demonstrate that the previously achieved 95% diffraction efficiency at a 1550 nm wavelength is also attainable with a reduced period of 3 μm. This smaller period is predicted to allow for spectral filtering, nearly equivalent to commercially available filters in terms of full width at half maximum (FWHM). Our findings underscore the potential of volumetric Si photonics and mark a significant step towards realizing 3D-integrated monolithic chips.