High field-effect mobility in n-channel Si face 4H-SiC MOSFETs with gate oxide grown on aluminum ion-implanted material

Gudjonsson, Gudjon; Ólafsson, Halldór; Allerstam, Fredrik; Nilsson, Per Åke; Sveinbjörnsson, Einar Ö.; Zirath, Herbert; Rödle, Thomas; Jos, Rik

doi:10.1109/led.2004.841191

Cited by 54 publications

(26 citation statements)

References 12 publications

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“…has been achieved by sodium-enhanced oxidation on the (0001) Si-face of 4H-SiC [5]. In addition, we have reported that the incorporation of phosphorus (P) into a SiO 2 /4H-SiC interface results in a low D it and a high field-effect mobility of up to 89 cm 2 V −1 s −1 on the (0001) Si-face of 4H-SiC [6].…”

Section: −1mentioning

confidence: 99%

“…It has been reported that NITs can be effectively removed by the incorporation of N [15], Na [16], K [17], and P [18] as revealed either by using low-temperature capacitance-voltage (C-V ) [15,18] or thermal dielectric relaxation current (TDRC) [16][17][18] measurements. It is interesting to note that improved field-effect mobilities can be obtained by utilizing oxides incorporating N [3,4], Na [5], and P [6], and thus we can assume that the NIT density is closely related to the field-effect mobility. This makes it also important to investigate the nature of NITs in B-incorporated MOS structures for a comprehensive understanding of the origin of interface states and the passivation mechanisms in the SiO 2 /4H-SiC interface structures.…”

Section: −1mentioning

confidence: 99%

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Effect of boron incorporation on slow interface traps in SiO2/4H-SiC structures

et al. 2017

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The reason for the effective removal of interface traps in SiO 2 /4H-SiC (0001) structures by boron (B) incorporation was investigated by employing lowtemperature electrical measurements. Low-temperature capacitance-voltage and thermal dielectric relaxation current measurements revealed that the density of electrons captured in slow interface traps in B-incorporated oxide is lower than that in dry and NO-annealed oxides. These results suggest that near-interface traps can be removed by B incorporation, which is considered to be an important reason for the increase in the field-effect mobility of 4H-SiC metal-oxide-semiconductor devices. A model for the passivation mechanism is proposed that takes account of stress relaxation during thermal oxidation.

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Section: −1mentioning

confidence: 99%

Section: −1mentioning

confidence: 99%

Effect of boron incorporation on slow interface traps in SiO2/4H-SiC structures

et al. 2017

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“…2 Although SiC is advantageous in that SiO 2 can be formed by oxidation, improvement of the SiO 2 /4H-SiC channel performance has plateaued, despite intensive research and development efforts. [3][4][5][6][7] Afanas'ev and Stesmans proposed that SiO 2 possesses traps near the conduction band edge of 4H-SiC, 8 which may cause the large interface states. Therefore, materials other than SiO 2 are worth considering.…”

Section: Introductionmentioning

confidence: 99%

Reduction of interface states by hydrogen treatment at the aluminum oxide/4H-SiC Si-face interface

2016

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Processes to form aluminum oxide as a gate insulator on the 4H-SiC Si-face are investigated to eliminate the interface state density (DIT) and improve the mobility. Processes that do not involve the insertion or formation of SiO2 at the interface are preferential to eliminate traps that may be present in SiO2. Aluminum oxide was formed by atomic layer deposition with hydrogen plasma pretreatment followed by annealing in forming gas. Hydrogen treatment was effective to reduce DIT at the interface of aluminum oxide and SiC without a SiO2 interlayer. Optimization of the process conditions resulted in DIT for the metal oxide semiconductor (MOS) capacitor of 1.7×1012 cm−2eV−1 at 0.2 eV, and the peak field-effect mobility of the MOS field-effect transistor (MOSFET) was approximately 57 cm2V−1s−1.

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“…The fact that gate oxide needs to be formed on the source region which usually has a substantial surface roughness due to the heavy dose nitrogen implantation and high-temperature annealing also gives rise to the concerns of gate oxide reliability. Recently, various approaches have been employed to improve the quality of the MOS interface [2][3][4][5][6][7]. Peak inversion channel mobilities of 50-70 cm 2 /V s [3,4] have been obtained by the nitridation of SiO 2 /SiC interface through nitric oxide (NO) growth or NO annealing.…”

Section: Introductionmentioning

confidence: 99%

“…Even higher inversion channel mobility up to 150 cm 2 /V s has been achieved by the use of contaminated alumina environment for gate oxidation [5]. However, there are problems associated with this special process: Rapid thermal annealing for ohmic contacts has to be avoided to attain the above results, or the channel mobility would be degraded by a factor of about two [6]; substantial mobile ions may have been introduced into gate oxide under the contaminated alumina environment [5]. In addition, some researchers utilized a buried channel structure formed by ion implantation to improve the channel mobility in 4H-SiC MOSFETs with up to 140 cm 2 /V s reported [7].…”

Section: Introductionmentioning

confidence: 99%