High-gain transimpedance amplifier in InP-based HBT technology for the receiver in 40-Gb/s optical-fiber TDM links

Mullrich, J.; Thurner, H.; Mullner, E.; Jensen, J.F.; Stanchina, W.E.; Kardos, M.; Rein, H.-M.

doi:10.1109/4.868033

Cited by 30 publications

(6 citation statements)

References 10 publications

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“…The size of is adjusted so that becomes times smaller. 1 To design the circuit, the input resistance, transimpedance gain and input-referred noise at low frequencies are where is assumed and will be validated later. To make the noise performance not worse than that of a commongate TIA, the sum of the noise from and (( 6)) is made equal to that from ((3)), which results in (7) Substituting ( 7) to (4), the design objective is to find the required that makes smaller than , which is the input resistance of the common-gate TIA.…”

Section: Amplifier Circuit Designmentioning

confidence: 99%

“…With , the tolerable input capacitance for (considering the 40 Gb/s data rate) is given by (23) In this design, with only 40 fF parasitic capacitance contributed by the active devices at the input, the tolerable photodiode capacitance is about 60-80 fF. 4 Since photodiodes with capacitance as low as 60 fF have been reported [1], [2], the bandwidth of the TIA will not be dominated by the input pole as long as the input resistance is kept lower than 50 .…”

Section: ) Reversed Triple-resonance Network (Rtrn)mentioning

confidence: 99%

“…The CDR circuit should extract the clock from the jittery incoming data while automatically retiming and de-multiplexing the data into lower-speed streams. Prior published 40 Gb/s amplifiers are either implemented in InP or SiGe technologies [1]- [4], or in CMOS but with limited gains [5]- [9]. On the other hand, existing 40 Gb/s CDRs either consume a significant amount of power or only provide moderate performance with respect to the recovered clock jitter [10]- [12].…”

Section: Introductionmentioning

confidence: 99%

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40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS

Liao

Liu

2008

IEEE J. Solid-State Circuits

106

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High-speed front-end amplifiers and CDR circuits play critical roles in broadband data receivers as the former needs to perform amplification at high data rate and the latter has to retime the data with the extracted low-jitter clock. In this paper, the design and experimental results of 40 Gb/s transimpedance-AGC amplifier and CDR circuit are described. The transimpedance amplifier incorporates reversed triple-resonance networks (RTRNs) and negative feedback in a common-gate configuration. A mathematical model is derived to facilitate the design and analysis of the RTRN, showing that the bandwidth is extended by a larger factor compared to using the shunt-series peaking technique, especially in cases when the parasitic capacitance is dominated by the next stage. Operating at 40 Gb/s, the amplifier provides an overall gain of 2 k and a differential output swing of 520mV pp with BER 10 9 for input spanning from 430 A pp to 4mA pp . The measured integrated input-referred noise is 3 3 A rms . The half-rate CDR circuit employs a direction-determined rotary-wave quadrature VCO to solve the bidirectional-rotation problem in conventional rotary-wave oscillators. This guarantees the phase sequence while negligibly affecting the phase noise. With 40 Gb/s 2 31 1 PRBS input, the recovered clock jitter is 0 7ps rms and 5 6ps pp . The retimed data exhibits 13 3ps pp jitter with BER 10 9 . Fabricated in 90 nm digital CMOS technology, the overall amplifier consumes 75 mW and the CDR circuit consumes 48 mW excluding the output buffers, all from a 1.2 V supply.

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Section: Amplifier Circuit Designmentioning

confidence: 99%

Section: ) Reversed Triple-resonance Network (Rtrn)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS

Liao

Liu

2008

IEEE J. Solid-State Circuits

106

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“…III–V compound semiconductors, such as indium phosphide, and their ternary and quaternary alloys, find extensive applications in high-speed integrated circuits, , photonic devices, and high-efficiency solar cells or artificial leaves for solar-to-hydrogen conversion, and they continue to be of great interest in contemporary fields of study, e.g., nanotechnological applications such as nanowires and quantum dots . Most of these devices are based on, often alloy-based, heterojunctions or quantum wells.…”

Section: Introductionmentioning

confidence: 99%

InP and AlInP(001)(2 × 4) Surface Oxidation from Density Functional Theory

et al. 2021

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The atomic structure and electronic properties of the InP and Al0.5In0.5P(001) surfaces at the initial stages of oxidation are investigated via density functional theory. Thereby, we focus on the mixed-dimer (2 × 4) surfaces stable for cation-rich preparation conditions. For InP, the top In–P dimer is the most favored adsorption site, while it is the second-layer Al–Al dimer for AlInP. The energetically favored adsorption sites yield group III–O bond-related states in the energy region of the bulk band gap, which may act as recombination centers. Consistently, the In p state density around the conduction edge is found to be reduced upon oxidation.

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“…With these high-performance technologies, optical circuits/devices for even higher data rate operations (e.g. SONET OC-768) have been reported [37][38][39][40][41][42]. However, the recent rapidly increasing demand for high volume, wide deployment of optical components in LAN, fiber-to-home, VSR and inter/intra-chip applications requires low-cost and low-power devices.…”

Section: List Of Figuresmentioning

confidence: 99%

Design of CMOS broadband transimpedance amplifiers for 10Gbit/s optical communications

Zheng¹

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High-gain transimpedance amplifier in InP-based HBT technology for the receiver in 40-Gb/s optical-fiber TDM links

Cited by 30 publications

References 10 publications

40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS

40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS

InP and AlInP(001)(2 × 4) Surface Oxidation from Density Functional Theory

Design of CMOS broadband transimpedance amplifiers for 10Gbit/s optical communications

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