High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors

Abstract

Recent safety standards set stringent requirements for the target fault coverage in embedded microprocessors, with the objective to guarantee robustness and functional safety of the critical electronic systems. This motivates the need for improving the quality of test generation for microprocessors. A new high-level implementationindependent test generation method for RISC processors is proposed. The set of instructions of the processor is partitioned into groups. For each group, a dedicated test template is created, to be used for generating two test programs, for testing the control and the data paths respectively. For testing the control part, a novel high-level control fault model is proposed. Using this model, a set of deterministic test data operands are generated for each instruction of the given group. The advantage of the high-level fault model is that it covers larger than SAF fault class including multiple fault coverage in the control part. For generating the data path test, pseudoexhaustive data operands are used. We investigated the feasibility of the approach and demonstrated high efficiency of the generated test programs for testing the execute module of the miniMIPS RISC processor. Keywords-RISC processors, high-level fault model, highlevel test generation, deterministic and pseudo-exhaustive tests, control and data path tests

Challenges of Reliability Assessment and Enhancement in Autonomous Systems

“…In other cases users resort to functional solutions, e.g. based on the so-called Self-Test Libraries [38], which rely on the Software-based Self-test approach [39], [40]. This solution seems particularly effective for in-field test of complex systems, since it allows to exploit self-test code provided by the developer of the modules composing the system and able to achieve a given fault coverage, which is integrated by the user into the application code and run when required to achieve the target reliability figures (e.g., at the Power-On, or periodically, or when specific error conditions happen).…”