High-Level Dataflow Programming for Reconfigurable Computing

Abstract

In many application domains, FPGAs are now promoted as a way of getting round the restrictions of specific CPU designs on system scalability. However, in the current state-of-the art, programming FPGAs remains essentially a hardware-oriented activity, relying on dedicated hardware description languages such as VHDL or Verilog. Using these languages requires expertise in digital design and in practice this limits the applicability of FPGA-based solutions. This is particulary true for stream-processing applications, in which some processing must be carried out "on the fly" on digital data streams. In this context, the dataflow programming model offers a very effective way to reduce the gap between high-level formulations and low-level implementations. To support this claim, the authors have recently introduced CAPH, a domain specific language, offering a fully-automated compilation path from high-level dataflow descriptions to FPGA configuration for stream-processing applications. This paper is a introduction to the CAPH language, giving its motivations and main design principles and exposing the basic features of its syntax, semantics and compilation. It also points to experimental results showing that, at least for stream-processing applications, the dataflow model of computation, used jointly as a programming model and an execution model, can offer a very effective way to conciliate abstraction and efficiency when programming FPGAs.

Dataflow Modeling for Reconfigurable Signal Processing Systems

“…A popular commercial HLS synthesizer is Vivado 3 from Xilinx, which accelerates IP creation by enabling C, C++ and System C specifications to be directly implemented into Xilinx programmable devices without the need to manually create the RTL description. Similarly, but based on dataflow approaches, Xronos [7] and the Caph compiler [59] are meant to provide dataflow-to-hardware generation. Xronos, which has been developed within RVC-CAL context where dataflow networks expressed using the CAL language based on the DPN MoC, is an evolution of the CAL2HDL framework and the work done in [56].…”

A Holistic Approach for Optimizing DSP Block Utilization of a CNN implementation on FPGA

“…The Hardware Automated Description Of CNNs (HADOC) utility is the tool proposed in this study for network exploration. Starting from a CNN description designed and learned using Caffe, HADOC generates the corresponding Caph [21] is a dataflow language used here as an intermediate representation between the Caffe CNN network and its hardware description in VHDL. It is an image processing specific High-Level Synthesis (HLS) that interprets a desired algorithm to create a digital hardware description that implements its behaviour.…”

Actors with stretchable access patterns

“…Nevertheless, it is not possible to translate all CAL programs into VHDL (or Verilog). Subset of CAL like RVC-CAL [3] or similar ones like CAPH [4]s o l v e this problem, mainly by setting constraints on the actor's description and assuming that they are linked with buffers. This is also the case of Floh language described in Ref.…”