High level design: a design vision for the 90's

Geus, Aart J. de

doi:10.1109/iccd.1992.276190

Cited by 3 publications

(2 citation statements)

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“…A clear trend towards reuse of existing designs is the emergence of parametric designs in standard libraries [13]. While such "families of circuits" have been already popular in the hardware verification community for years, where they are the best examples for induction-based reasoning in the hardware application domain, industrial practice did not feature parametric designs in standard libraries because of lack of consolidated methods for their lull-automatic treatment in the design lifecycle.…”

Section: Motivationmentioning

confidence: 99%

Fully automatic verification and error detection for parameterized iterative sequential circuits

Margaria

1996

Tools and Algorithms for the Construction and Analysis of Systems

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The paper shows how iterative parametric sequential circuits, which are most relevant in practice, can be verified fully automatically. Key observation is that monadic second-order logic on strings provides an adequate level for hardware specification and implementation. This allows us to apply the corresponding decision procedure and counter-model generator implemented in the Mona verification tool, which, for the first time, yields 'push-button' verification, and error detection and diagnosis for the considered class of circuits. As illustrated by means of various versions of counters, this approach captures hierarchical and mixed mode verification, as well as the treatment of varying connectivity in iterative designs. MotivationA clear trend towards reuse of existing designs is the emergence of parametric designs in standard libraries [13]. While such "families of circuits" have been already popular in the hardware verification community for years, where they are the best examples for induction-based reasoning in the hardware application domain, industrial practice did not feature parametric designs in standard libraries because of lack of consolidated methods for their lull-automatic treatment in the design lifecycle. Thus the pressure towards fully automated methods for the analysis, verification, and fault detection of parametric circuits and their specifications grows with the increasing demand for design reuse. Unfortunately, the standard automata theoretic techniques of the hardware community fail here, because the treatment of automata of unbounded size is required. At this stage, Basin and Klarlund discovered that monadic second-order logic on strings, although 'hopeless' from the complexity point of view, is well-behaved in many practical applications, and, in particular, well-suited for the fully automatic verification of *Fakult~t f'dr Mathematik und Informatik, Universitiit Passau, Innstr. 33, 94032 Passau (D), tel: +49 851 509.3096, fax: +49 851 509.3092, ~iziana@fmi.tmi-paasau.dl

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Section: Motivationmentioning

confidence: 99%

Fully automatic verification and error detection for parameterized iterative sequential circuits

Margaria

1996

Tools and Algorithms for the Construction and Analysis of Systems

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“…circuits where the structure can be described inductively (iterativeiy, or recursiveiy) in terms of size parameters. Since reuse of existing designs has become an important issue in practice, use of parametric designs in the form of standard libraries has been emphasized as an emerging trend [12]. By directly addressing the issue of parameterization in our approach, as described in this paper, we provide the necessary framework for representation and verification of such designs.…”

Section: Introductionmentioning

confidence: 99%

Parametric circuit representation using inductive Boolean functions

Gupta

Fisher

1993

Computer Aided Verification

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We have developed a methodology based on symbolic manipulation of induefive Boolean functions (IBFs) for formal verification of inductively-defined hardware. This methodology combines the techniques of reasoning by induction and symbolic tautologychecking in an automated and potentially efficient way. In this paper, we describe a component of this methodology that regards varioes mechanisms used to represent inductivelydefined circuits in the form of IBFs. The focus is on general parameterization issues, such as multiple parameter functions, multiple output functions, interaction of different parameters for supporting compositions etc. These mechanisms, which may be useful in other applications involving parametric circuit descriptions, are KlusU'ated through practical circuit examples along with preliminary results. We also describe an application of our formal verification methodology, where a proof by induction is performed by automatic symbolic manipulation of parametric circuit representations.

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Representation and symbolic manipulation of linearly inductive Boolean functions

Gupta¹,

Fisher²

Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)

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High level design: a design vision for the 90's

Cited by 3 publications

References 0 publications

Fully automatic verification and error detection for parameterized iterative sequential circuits

Fully automatic verification and error detection for parameterized iterative sequential circuits

Parametric circuit representation using inductive Boolean functions

Representation and symbolic manipulation of linearly inductive Boolean functions

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