High level Hardware/Software Communication Estimation in Shared Memory Architecture

Pandey, Sujan; Zimmer, H.; Glesner, Manfred; Mühlhäuser, Max

doi:10.1109/iscas.2005.1464518

Cited by 6 publications

(3 citation statements)

References 6 publications

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“…(18). The communication task c ∈ C with ALAP time ALAPc cannot be executed later than Ψ, when the data is transferred through a bus b of type r with the communication lifetime interval of a task CLT Ic,r,V .…”

Section: Bus Synthesis and Optimizationmentioning

confidence: 99%

“…Considering these trends, synthesizing an energy efficient on-chip communication bus is a challenging task to the system designers. The early work about communication bus synthesis focused mainly on minimizing bus width [17], [19] protocol selection [6], [13], interface synthesis [18], and synthesis of single global bus topology [9]. In [23] an automatic bus generation for a MPSoC was proposed.…”

Section: Introductionmentioning

confidence: 99%

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Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint

Pandey

Glesner

2006

Proceedings of the 43rd Annual Conference on Design Automation - DAC '06

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We propose a statistical approach for minimizing on-chip communication bus width and number of buses with reduced communication energy under timing yield constraint. The slack is exploited to maximize sharing of buses and to reduce energy by simultaneously scaling the voltage during the communication synthesis. Because of the diversity of applications to be run on a single SoC, there exists variability of data size to be transferred among the on-chip communicating modules. This variability of data size is modeled as a normally distributed random variable. The resulting synthesis problem is relaxed to the convex quadratic optimization problem and is solved efficiently using a convex optimization tool. The effectiveness of our approach is demonstrated by applying optimization to an automatically generated benchmark and a real-life application. By varying the value of timing yield constraint, a trade-off between minimization of buses and energy reduction is explored. The experimental results show the significant reduction of communication energy with the increasing timing yield. However, the timing yield offers a limitation to minimize the size of bus width and number of buses, if the yield is increased beyond a certain limit.

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Section: Bus Synthesis and Optimizationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint

Pandey

Glesner

2006

Proceedings of the 43rd Annual Conference on Design Automation - DAC '06

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“…Givargis et al [7] explore a design space with multiple communication channels and several bus encoding schemes and try to find the bus width that minimizes the power consumption under such constraints. Similarly, Pandey et al [17] presents a hardware/software partitioning framework where an application is partitioned into several communicating processes through shared memory. They optimize the communication delay between processes for a given bus width and buffer size.…”

Section: Related Workmentioning

confidence: 99%

Estimating data bus size for custom processors in embedded systems

Özer

Nisbet

Gregg

et al. 2005

Des Autom Embed Syst

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We propose a method to estimate the data bus width to the requirements of an application that is to run on a custom processor. The proposed estimation method is a simulationbased tool that uses Extreme Value Theory to estimate the width of an off-chip or on-chip data bus based on the characteristics of the application. It finds the minimum number of bus lines needed for the bus connecting the custom processor to other units so that the probability of a multicycle data transfer on the bus is extremely unlikely. The potential target platforms include embedded systems where a custom processor (i.e. an ASIC or a FPGA) in a system-on-a-chip or a system-on-a-board is connected to memory, I/O and other processors through a shared bus or through point-to-point links. Our experimental and analytical results show that our estimation method can reduce the data bus width and cost by up to 66% with an average of 38% for nine benchmarks. The narrower data bus allows us to increase the spacing between the bus lines using the silicon area freed from the eliminated bus lines. This reduces interwire capacitance, which in turn leads to a significant reduction of bus energy consumption. Bus energy can potentially be reduced up to 89% for on-chip data buses with an average of 74% for seven benchmarks. Also, reduction in the interwire capacitance improves the bus propagation delay and on-chip bus propagation delay can be reduced up to 68% with an average of 51% for seven benchmarks using a narrower custom data bus.

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Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint

Pandey¹,

Glesner²

2006

2006 43rd ACM/IEEE Design Automation Conference

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High level Hardware/Software Communication Estimation in Shared Memory Architecture

Cited by 6 publications

References 6 publications

Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint

Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint

Estimating data bus size for custom processors in embedded systems

Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint

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