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Abstract-The advancement in process technology has made it possible to integrate multiple processing modules on a single chip. As a result of this, there is a sharp increase of communication traffic on the communication bus architecture. In this case, the traditional single bus based architecture may fail to meet the real-time constraints. The major concern of the scaled technology is an effect of coupling capacitance due to the trend of shrinking pitches, i.e., the distance between two wires. Its consequence is higher crosstalk noise, which degrades the signal integrity and modifies the power consumption of the wires. This motivates the synthesis of a custom on-chip bus architecture, which is efficient in terms of power and performance. Further, the memory of a complex multiprocessor system has a significant contribution to power and delay.In this paper, we present a co-synthesis of on-chip buses and memories, which finds an optimal bus architecture, memory sizes, and the number of memories. The bus synthesis problem is formulated as an optimization problem as proposed in [11], [9]. Then it is solved efficiently using an optimization tool. The memory synthesis problem is based on the graph partitioning algorithm, which partitions a data dependency task graph into a set of sub graphs with the minimum number of data dependencies called cut. The experiments carried out on the real-life multimedia applications validate the proposed technique for the co-synthesis of bus architecture and memory.

In this paper, we present a bus and memory architectures co-synthesis technique. The co-synthesis problem is formulated as an optimization problem, where scheduling, allocation, and binding of tasks are done simultaneously in order to optimize the bus widths, the number of buses, and the memory sizes. As a main contribution, bus and memory architectures are optimized simultaneously by allocating different amount of slacks to them during co-synthesis. The method finds a balance of slack allocation for both bus and memory optimization. While the previous co-synthesis approaches do not consider the slack allocation technique, the synthesized bus and memory architectures will not be optimal in terms of area and energy consumption. The experimental results carried out on real-life applications show 19% and 24% reduction in bus and memory area, respectively and 37% reduction in energy overhead due to a bridge in compared to the previous co-synthesis approach.

AbstrueAfter the partitioning in Hw/Sw codesign, an efficient mapping of hardware components to the target architectures fulfilling both power and delay requirements are still a challenging task for P system designer. In this paper, high IWEI power/delay estimation to map hardware components to the target architectures based on petri net is proposed, which helps designers to model hardware architecture at high level and estimates power and delay €or several design alternatives. This estimation shows how various solutions are distributed over the entire design space and helps to 6nd an optimal solution. In this approach, we first extract parqeters such as capacitances and resistances of a gate from the transistor level and form B library of basic components such as adder, multiplier, FIFO etc. or seberal sizes with their corresponding powerldelay informations. We model a hardware architecture in petri net by taking necessary components from the library and estimate powerldelay for several design atternntives. For an experimental purpose, we model a FFT hardware architecture and the results clearly demonstrate the utility of our techniques for the mapping of hardware based on power/delay informations