Slack allocation based co-synthesis and optimization of bus and memory architectures for MPSoCs

Abstract

In this paper, we present a bus and memory architectures co-synthesis technique. The co-synthesis problem is formulated as an optimization problem, where scheduling, allocation, and binding of tasks are done simultaneously in order to optimize the bus widths, the number of buses, and the memory sizes. As a main contribution, bus and memory architectures are optimized simultaneously by allocating different amount of slacks to them during co-synthesis. The method finds a balance of slack allocation for both bus and memory optimization. While the previous co-synthesis approaches do not consider the slack allocation technique, the synthesized bus and memory architectures will not be optimal in terms of area and energy consumption. The experimental results carried out on real-life applications show 19% and 24% reduction in bus and memory area, respectively and 37% reduction in energy overhead due to a bridge in compared to the previous co-synthesis approach.

System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC

“…Pasricha et al [4] proposed an integrated heuristic approach for memory and bus matrix synthesis that was also primarily aimed at data blocks. Pandey et al [8] presented a bus and data memory architecture co-synthesis approach based on slack allocation. Issenin et al [5] proposed a MILP and heuristic memory synthesis approaches that utilized a fixed topology bus architecture and aimed at minimizing data memory usage.…”