Architecture level design space exploration and mapping of hardware

Abstract

AbstrueAfter the partitioning in Hw/Sw codesign, an efficient mapping of hardware components to the target architectures fulfilling both power and delay requirements are still a challenging task for P system designer. In this paper, high IWEI power/delay estimation to map hardware components to the target architectures based on petri net is proposed, which helps designers to model hardware architecture at high level and estimates power and delay €or several design alternatives. This estimation shows how various solutions are distributed over the entire design space and helps to 6nd an optimal solution. In this approach, we first extract parqeters such as capacitances and resistances of a gate from the transistor level and form B library of basic components such as adder, multiplier, FIFO etc. or seberal sizes with their corresponding powerldelay informations. We model a hardware architecture in petri net by taking necessary components from the library and estimate powerldelay for several design atternntives. For an experimental purpose, we model a FFT hardware architecture and the results clearly demonstrate the utility of our techniques for the mapping of hardware based on power/delay informations

A Model-based Approach to Realize Privacy and Data Protection by Design

“…Last, the refined Processes are manually allocated among components. The referred allocation is part of the so called design space exploration problem [15]: the design space is generated by the possible distributions of Processes among architectural components (NP-hard problem).…”