High-level modeling and FPGA prototyping of microprocessors

Abstract

Emerging high-level hardware description and synthesis technologies in conjunction with field-programmable gate arrays (FPGAs) have significantly lowered the threshold for hardware development. Opportunities exist to integrate these technologies into a tool for exploring and evaluating microarchitectural designs. This paper presents a case study in developing the synthesizable high-level model of a superscalar processor and producing a working prototype in FPGA. Using an experimental operation-centric hardware description language, we have created the synthesizable model of a superscalar speculative out-of-order core for the integer subset of SimpleScalar PISA. A prototype implementation is produced by synthesizing the high-level model for the Spyder FPGA prototyping board. In addition, we have modified the baseline processor model to create derivative processor designs that add newly proposed experimental mechanisms. The derivative models are useful both in testing the completeness and correctness of new mechanisms and in assessing the mechanisms' impact on implementation area and cycle time.

A-Port Networks

“…Early efforts at creating performance models on FPGAs such as Ray and Hoe [2003] and Wunderlich and Hoe [2004] shared the goal of creating a model early in the design process, but these efforts used the FPGA clock itself as the simulation clock, reducing fidelity in order to ease development time and save FPGA resources. Thus these are more closely aligned with what we have termed a direct emulation approach.…”

Microcontroller Based Testing of Digital IP-Core

“…The later has an advantage over the former as it is cost effective and faults are removed at design stage whereas in the former it is not possible to do so.FPGA, also called VLSI breadboard, is chosen for implementing IP-Core, providing flexibility in the design. Working prototype of microprocessor is developed in [4]. The FPGA technology is commonly used for circuit emulation.…”

Using static analysis for coverage extraction fromemulation/prototyping platforms

“…Full-system simulation based verification with real-world workloads running on the underlying hardware designs has become extremely time consuming. Emulation/prototyping, such as that based on Field Programmable Gate Array (FPGAs) platforms, has emerged as a prominent technique to accelerate verification in recent years [2][3][4][5]. The primary motivation for using these alternative platforms is speed: runtime of a test during emulation is orders of magnitude lower compared to simulation [2].…”