High-Level Synthesis for Semi-Global Matching: Is the Juice Worth the Squeeze?

Qamar, Affaq; Muslim, Fahad Bin; Gregoretti, Francesco; Lavagno, Luciano; Lazarescu, Mihai T.

doi:10.1109/access.2016.2635378

Cited by 14 publications

(9 citation statements)

References 30 publications

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“…We also plan to use high-level synthesis (HLS) techniques to implement the NN on FPGA to explore more architectures and computational models (e.g., vectorization) and compare HLS implementation quality and manual optimization [50].…”

Section: Discussionmentioning

confidence: 99%

Very Low Power Neural Network FPGA Accelerators for Tag-Less Remote Person Identification Using Capacitive Sensors

et al. 2019

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Human detection, identification, and monitoring are essential for many applications aiming to make smarter the indoor environments, where most people spend much of their time (like home, office, transportation, or public spaces). The capacitive sensors can meet stringent privacy, power, cost, and unobtrusiveness requirements, they do not rely on wearables or specific human interactions, but they may need significant on-board data processing to increase their performance. We comparatively analyze in terms of overall processing time and energy several data processing implementations of multilayer perceptron neural networks (NNs) on board capacitive sensors. The NN architecture, optimized using augmented experimental data, consists of six 17-bit inputs, two hidden layers with eight neurons each, and one four-bit output. For the software (SW) NN implementation, we use two STMicroelectronics STM32 low-power ARM microcontrollers (MCUs): one MCU optimized for power and one for performance. For hardware (HW) implementations, we use four ultralow-power field-programmable gate arrays (FPGAs), with different sizes, dedicated computation blocks, and data communication interfaces (one FPGA from the Lattice iCE40 family and three FPGAs from the Microsemi IGLOO family). Our shortest SW implementation latency is 54.4 µs and the lowest energy per inference is 990 nJ, while the shortest HW implementation latency is 1.99 µs and the lowest energy is 39 nJ (including the data transfer between MCU and FPGA). The FPGAs active power ranges between 6.24 and 34.7 mW, while their static power is between 79 and 277 µW. They compare very favorably with the static power consumption of Xilinx and Altera low-power device families, which is around 40 mW. The experimental results show that NN inferences offloaded to external FPGAs have lower latency and energy than SW ones (even when using HW multipliers), and the FPGAs with dedicated computational blocks (multiply-accumulate) perform best.INDEX TERMS Indoor person identification, capacitive sensing, neural networks, hardware design, ultralow power FPGAs, hardware acceleration, embedded design optimization.

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Section: Discussionmentioning

confidence: 99%

Very Low Power Neural Network FPGA Accelerators for Tag-Less Remote Person Identification Using Capacitive Sensors

et al. 2019

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“…The concept of auto-generating HDL from various high level programs in nothing new as tools like Xilinx System Generator and Mathworks HDL Coder have been around since 2012. In the mid 2010s Qamar et al showcased the usability of high level synthesis and its competitive abilities against traditional manually coded designs [16] [17]. An integrated tool flow for simulating and generating HDL for computer vision algorithms was created in 2019 with the advent of the Vision HDL Toolbox which allows one to convert images composed of rows and columns into pixel streams that can be processed at the pixel line rates.…”

Section: Related Workmentioning

confidence: 99%

“…Therefore the mapping must be split up to the surrounding 4 pixels via a process known as bilinear interpolation. The interpolation is shown in (14)(15)(16)(17) and shows how a point (u, v) is represented by the surrounding pixels G 0 , G 1 , G 2 , G 3 utilizing deltaU and deltaV which describe the location of the sub-pixel in relation to the nearest pixels.…”

Section: Undistortionmentioning

confidence: 99%

Model Based Design of a Real Time FPGA-Based Lens Undistortion and Image Rectification Algorithm for Stereo Imaging

Kaputa

Derhak

2023

IEEE Access

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Low cost imaging sensors and powerful embedded computers have taken the field of computer vision to new heights. One of the challenges that remains is to shorten the development time that it takes to target one's algorithm to hardware. This work details the steps necessary to use Model Based Design to first simulate and then to target a stereo rectification and undistortion algorithm to an embedded FPGA system on chip hardware target. This work demonstrates what the future of FPGA-based algorithm development might look like by making use of closed loop design techniques with the aid of novel Model Based Design tool flows. Hardware-abstracted constructs such as 'virtual cameras' and the capability of pulling images off the target system and feeding them back into the simulation model help to minimize discrepancies between simulation and hardware domains, ultimately reducing the total development time. The developed system is a deterministic real time and low latency implementation as it does not rely on external off chip memory as all necessary buffering is done in the internal FPGA block RAM structures. The design is capable of processing 752x480 images at pixel line rates and is easily expandable to high resolution images. The algorithm being developed is not being touted as novel, rather that it is sufficiently complex in order to demonstrate the power of the Model Based Design tool flows.

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“…For reducing computational complexity, two SGM methods based on the coarse-to-fine strategy are proposed in [25], [26]. Moreover, original or variant methods of SGM have been implemented on different computing architectures such as Graphics Processing Unit (GPU) [27], Field-Programmable Gate Array (FPGA) [28], and other embedded devices [29]. Although the SGM method has been widely used, this method may yield the known streaking artifacts.…”

Section: A Related Workmentioning

confidence: 99%

An Efficient Dense Stereo Matching Method for Planetary Rover

Chen

2019

IEEE Access

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Stereo matching is one of the most important and challenging subjects in the field of planetary rover with a stereo vision system. The generated disparity map can make rover to avoid the obstacle and explore the planetary surface automatically. In this paper, we propose an efficient dense stereo matching method to generate disparity maps for a planetary rover, which relies on 3-D plane fitting, adaptive penalties, and coarse-to-fine disparity constraint. In order to achieve efficient stereo matching at the coarsest level of the pyramid, we present a 3-D plane fitting to reduce the disparity search range and propose adaptive penalties in the more-global matching method for obtaining an accurate disparity map. At the finer level, our method then estimates the disparity search range based on coarse-to-fine disparity constraint and utilizes adaptive penalties to obtain an accurate disparity map. The extensive experiments with stereo images of Chang'e-3 rover demonstrate that our approach can generate disparity maps efficiently and accurately compared with the most state-of-the-art semi-global matching methods, especially at low texture regions, depth discontinuities, and occlusion regions. INDEX TERMS Stereo matching, disparity map, coarse-to-fine architecture, 3-D plane, planetary rover.

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High-Level Synthesis for Semi-Global Matching: Is the Juice Worth the Squeeze?

Cited by 14 publications

References 30 publications

Very Low Power Neural Network FPGA Accelerators for Tag-Less Remote Person Identification Using Capacitive Sensors

Very Low Power Neural Network FPGA Accelerators for Tag-Less Remote Person Identification Using Capacitive Sensors

Model Based Design of a Real Time FPGA-Based Lens Undistortion and Image Rectification Algorithm for Stereo Imaging

An Efficient Dense Stereo Matching Method for Planetary Rover

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