2015
DOI: 10.1155/2015/870569
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High Level Synthesis FPGA Implementation of the Jacobi Algorithm to Solve the Eigen Problem

Abstract: We present a hardware implementation of the Jacobi algorithm to compute the eigenvalue decomposition (EVD). The computation of eigenvalues and eigenvectors has many applications where real time processing is required, and thus hardware implementations are often mandatory. Some of these implementations have been carried out with field programmable gate array (FPGA) devices using low level register transfer level (RTL) languages. In the present study, we used the Xilinx Vivado HLS tool to develop a high level sy… Show more

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Cited by 13 publications
(3 citation statements)
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“…For Hermitian matrices, which is the case of R Y , algorithms that are mostly used are the QR algorithm (for matrices with order m ≤ 25) [12], and the Lanczos algorithm (for moderated-to-high values of m, less than a few thousands) [11], [13]. The Jacobi algorithm is another well-known alternative; it has been considered in microchip implementations [14] in the context of eigenvalue-based spectrum sensing [15].…”
Section: B Problem Descriptionmentioning
confidence: 99%
“…For Hermitian matrices, which is the case of R Y , algorithms that are mostly used are the QR algorithm (for matrices with order m ≤ 25) [12], and the Lanczos algorithm (for moderated-to-high values of m, less than a few thousands) [11], [13]. The Jacobi algorithm is another well-known alternative; it has been considered in microchip implementations [14] in the context of eigenvalue-based spectrum sensing [15].…”
Section: B Problem Descriptionmentioning
confidence: 99%
“…In recent years, there has been intense interest for emerging applications in embedded systems, such as multiple-input multiple-output (MIMO) systems [36,37], data analytics [38][39][40][41], sparse representation of signals [42][43][44][45][46][47], that require efficient SVD algorithms. Since SVD algorithms reduce to solve an eigenvalue problem, that is computationally expensive, both specific hardware solutions [48][49][50][51][52][53][54][55][56] and parallel implementations [57,58] have been proposed to overcome this bottleneck.…”
Section: Introductionmentioning
confidence: 99%
“…Regarding more complex architectures, there is a rich literature on how to implement mathematical algorithms on Field Programmable Gate Arrays (FPGAs) and other programmable hardware [53][54][55][56]. Those are generally sophisticated and expensive systems, used for high-end applications and exploiting a completely different computation model, based on massive parallelism.…”
Section: Introductionmentioning
confidence: 99%