High-level synthesis of data paths with concurrent error detection

Antola, A.; Piuri, Vincenzo; Sami, Mariagiovanna

doi:10.1109/dftvs.1998.732178

Cited by 26 publications

(13 citation statements)

References 10 publications

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“…Our work, in contrast, focuses on minimizing area under performance and reliability constraints using components with the same reliability characterizations. Antola et al [6] present an HLS heuristic that applies reliability by selectively replicating parts of the datapath for selfchecking as an error-detection measure. Our heuristic differs by applying reliability through TMR with resource sharing.…”

Section: Related Workmentioning

confidence: 99%

“…Similarly, high-level synthesis for ASICs has introduced conceptually similar techniques [6], but whereas ASIC approaches must deal with transient errors, FPGAs must pay special attention to SEU in configuration memory that will remain until scrubbing or reconfiguration (referred to as semipermanent errors for simplicity). Due to these semipermanent errors, FPGA approaches require significantly different HLS strategies.…”

Section: Introductionmentioning

confidence: 99%

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A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

Wilson

Shastri

Stitt

2017

International Journal of Reconfigurable Computing

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Computing systems with field-programmable gate arrays (FPGAs) often achieve fault tolerance in high-energy radiation environments via triple-modular redundancy (TMR) and configuration scrubbing. Although effective, TMR suffers from a 3x area overhead, which can be prohibitive for many embedded usage scenarios. Furthermore, this overhead is often worsened because TMR often has to be applied to existing register-transfer-level (RTL) code that designers created without considering the triplicated resource requirements. Although a designer could redesign the RTL code to reduce resources, modifying RTL schedules and resource allocations is a time-consuming and error-prone process. In this paper, we present a more transparent high-level synthesis approach that uses scheduling and binding to provide attractive tradeoffs between area, performance, and redundancy, while focusing on FPGA implementation considerations, such as resource realization costs, to produce more efficient architectures. Compared to TMR applied to existing RTL, our approach shows resource savings up to 80% with average resource savings of 34% and an average clock degradation of 6%. Compared to the previous approach, our approach shows resource savings up to 74% with average resource savings of 19% and an average heuristic execution time improvement of 96x.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

Wilson

Shastri

Stitt

2017

International Journal of Reconfigurable Computing

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“…Assume that the output of fu 1 is used by the island i 2 . Let T clk be the given clock period and we assume that d(fu 1 …”

Section: Problem Formulationmentioning

confidence: 99%

“…CED can reduce overheads significantly compared with TMR. Antola, et al 1) proposed an Force-Directed Scheduling (FDS) based fault-secure scheduling algorithm to minimize area overheads. Since this approach does not break a recomputation CDFG, the resultant latency or area overhead may increase.…”

Section: Introductionmentioning

confidence: 99%

A Fault-Secure High-Level Synthesis Algorithm for RDR Architectures

Tanaka

Yanagisawa

Ohtsuki

et al. 2011

IPSJ Transactions on System LSI Design Methodology

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As device feature size decreases, the reliability improvement against soft errors becomes quite necessary. A fault-secure system, in which concurrent error detection is realized, is one of the solutions to this problem. On the other hand, average interconnection delays exceed gate delays which leads to a serious timing closure problem. By using regular-distributed-register architecture (RDR architecture), we can estimate interconnection delays very accurately and their influence can be much reduced even in behavioral-level design. In this paper, we propose a fault-secure high-level synthesis algorithm for an RDR architecture. In fault-secure high-level synthesis, a recomputation CDFG as well as a normal-computation CDFG must be scheduled to control steps and bound to functional units. Firstly, our algorithm re-uses vacant areas on RDR islands to allocate new function units additionally for the recomputation CDFG. Secondly, we propose an efficient edge-break algorithm which considers comparison nodes' scheduling/binding. We can have small-latency scheduling/binding for both the normal CDFG and recomputation CDFG. Our algorithm reduces the required control steps by up to 53% compared with the conventional approach.

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“…A recent survey on circuit/logic level CED techniques can be found at [18]. Recently, many CED techniques that exploit RT level scheduling and binding are proposed to achieve better CED capability with less overhead [13][14] [19][20] [21]. RT-level CED techniques use either space redundancy, or time redundancy, or both (hybrid redundancy).…”

Section: Fault Tolerancementioning

confidence: 99%

An ILP formulation to Unify Power Efficiency and Fault Detection at Register-Transfer Level

Liu

2009

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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As the integration level and clock speed of VLSI devices keep rising, power consumption of those devices increases dramatically. At the same time, shrinking size of transistors that enables denser and smaller chips running at faster clock speeds makes devices more susceptible to environment-induced faults. Both power reduction and concurrent error detection are becoming enabling technologies in Very Deep Sub Micron and nanometer technology domains. However, existing techniques either minimize power of "fault-free" devices, or improve fault tolerance without concerning power. Little work has been proposed to optimize the two objectives simultaneously. In this paper we attack this problem by unifying power efficiency and fault tolerance in a comprehensive Integer Linear Programming formulation. The proposed approach is tested using known benchmarks. MotivationOver the past decades significant technological progress has been made in Very Deep Sub-Micron (VDSM) and nanometer technology domains. However, the performance improvement due to shrinking size of transistors that enables denser and smaller chips running at faster clock speeds and consuming less power has come at the cost of decreased reliability, as warned by the International Technology Roadmap of Semiconductors (ITRS). Besides inherent design defects such as ground bounce, IR drop, leakage, and charge sharing, densely packed chips are also highly susceptible to environment-induced Single Event Upsets (SEU) and Single Event Latchups (SEL). To compensate for the inevitable increase of failures, and to avoid revenue losses, yield reduction, and time-to-market slowdown, the ITRS urges "automatic insertion of robustness into the design." On the other hand, design for power efficiency is now a domain under intensive research due to increased chip density and clock frequency. Power reduction techniques can help reduce power dissipation, extend battery lifetime, improve noise margin, and reduce packaging and cooling cost.However, until recently little research has been done to jointly consider both fault tolerance and power efficiency. This is mainly due to the direct conflict between the two objectives, as fault tolerance is usually achieved through redundancy (space, time, or information), and a redundant system unavoidably consumes more power than its non-redundant version. This conflict must be addressed properly since the need for power efficiency and fault tolerance continues rising while the demand for faster and better systems never stops. However, since the techniques for the two design objectives are developed independently, they inevitably achieve one but fail the other. For example, exploiting Register-Transfer (RT) level operation-to-cycle schedule and operation-to-unit binding to reduce switching activities will tend to disturb the schedule and binding tuned for fault detection, and vice versa. Further, the existing power-reduction techniques do not exploit the unique characteristics of faults and redundant computations, and will not result in good q...

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High-level synthesis of data paths with concurrent error detection

Cited by 26 publications

References 10 publications

A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

A Fault-Secure High-Level Synthesis Algorithm for RDR Architectures

An ILP formulation to Unify Power Efficiency and Fault Detection at Register-Transfer Level

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