High-level synthesis of dataflow programs for signal processing systems

Bezati, Endri; Mattavelli, Marco; Janneck, Jörn W.

doi:10.1109/ispa.2013.6703837

Cited by 25 publications

(15 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Their tool generates VHDL, however, it lacks loop support. Bezati et al [53] developed Xronos, aiming to support the ISO subset of CAL actor language to generate RTL code. Xronos uses OpenForge and generates Verilog, similar to CAL2HDL, however the authors claimed that Xronos operates faster and the generated hardware uses fewer resources because of changes in the transformations applied to the IR that is used as the input to the OpenForge.…”

Section: Related Workmentioning

confidence: 99%

Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs

2018

View full text Add to dashboard Cite

The last ten years have seen performance and power requirements pushing computer architectures using only a single core towards so-called manycore systems with hundreds of cores on a single chip. To further increase performance and energy efficiency, we are now seeing the development of heterogeneous architectures with specialized and accelerated cores. However, designing these heterogeneous systems is a challenging task due to their inherent complexity. We proposed an approach for designing domain-specific heterogeneous architectures based on instruction augmentation through the integration of hardware accelerators into simple cores. These hardware accelerators were determined based on their common use among applications within a certain domain.The objective was to generate heterogeneous architectures by integrating many of these accelerated cores and connecting them with a network-on-chip. The proposed approach aimed to ease the design of heterogeneous manycore architectures-and, consequently, exploration of the design space-by automating the design steps. To evaluate our approach, we enhanced our software tool chain with a tool that can generate accelerated cores from dataflow programs. This new tool chain was evaluated with the aid of two use cases: radar signal processing and mobile baseband processing. We could achieve an approximately 4× improvement in performance, while executing complete applications on the augmented cores with a small impact (2.5-13%) on area usage. The generated accelerators are competitive, achieving more than 90% of the performance of handwritten implementations.

show abstract

Section: Related Workmentioning

confidence: 99%

Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs

2018

View full text Add to dashboard Cite

show abstract

“…Example of saliency maps computed by the original model and our scaled down dataflow-based implemention: row1: original image, row2: ground truth, row3: saliency map generated using the original algorithm and row4: the thresholded saliency map generated by our dataflow implementation. Using the ORCC-CAL compiler framework, we produce two types of output from the DPN: a) C code targeting multicore CPUs and b) Verilog code targeting FPGAs with the CAL-Xronos toolchain [18]. The former is used to verify the functional correctness of implementation and generate results, while the latter is used as a part of our smart camera architecture development on FPGA.…”

Section: B Algorithmic Implementation Using Dataflow Designmentioning

confidence: 99%

Power efficient dataflow design for a heterogeneous smart camera architecture

Bhowmik

Garcia

Wallace

et al. 2017

2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)

View full text Add to dashboard Cite

Abstract-Visual attention modelling characterises the scene to segment regions of visual interest and is increasingly being used as a pre-processing step in many computer vision applications including surveillance and security. Smart camera architectures are an emerging technology and a foundation of security and safety frameworks in modern vision systems. In this paper, we present a dataflow design of a visual saliency based camera architecture targeting a heterogeneous CPU+FPGA platform to propose a smart camera network infrastructure. The proposed design flow encompasses image processing algorithm implementation, hardware & software integration and network connectivity through a unified model. By leveraging the properties of the dataflow paradigm, we iteratively refine the algorithm specification into a deployable solution, addressing distinct requirements at each design stage: from algorithm accuracy to hardware-software interactions, real-time execution and power consumption. Our design achieved real-time run time performance and the power consumption of the optimised asynchronous design is reported at only 0.25 Watt. The resource usages on a Xilinx Zynq platform remains significantly low.

show abstract

“…To target FPGAs, the mean shift derivations are compiled with Orcc using Xronos [3], a Verilog backend that generates an FPGA hardware design from the application. The Xilinx ISE software is used to synthesise the Verilog for the Xilinx XC72100-2FFG1156 board, which has 554800 Slice Registers, 277400 Slice LUTs, 755 BRAMs and 2020 DSPs.…”

Section: Target Specific Mean Shift Optimisationmentioning

confidence: 99%

Profile Guided Dataflow Transformation for FPGAs and CPUs

Stewart

Bhowmik

Wallace

et al. 2015

J Sign Process Syst

View full text Add to dashboard Cite

This paper proposes a new high-level approach for optimising field programmable gate array (FPGA) designs. FPGA designs are commonly implemented in low-level hardware description languages (HDLs), which lack the abstractions necessary for identifying opportunities for significant performance improvements. Using a computer vision case study, we show that modelling computation with dataflow abstractions enables substantial restructuring of FPGA designs before lowering to the HDL level, and also improve CPU performance. Using the CPU transformations, runtime is reduced by 43%. Using the FPGA transformations, clock frequency is increased from 67MHz to 110MHz. Our results outperform commercial low-level HDL optimisations, showcasing dataflow program abstraction as an amenable computation model for highly effective FPGA optimisation.

show abstract

High-level synthesis of dataflow programs for signal processing systems

Cited by 25 publications

References 16 publications

Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs

Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs

Power efficient dataflow design for a heterogeneous smart camera architecture

Profile Guided Dataflow Transformation for FPGAs and CPUs

Contact Info

Product

Resources

About