High-level synthesis under I/O Timing and Memory constraints

Coussy, Philippe; Corre, Gwenolé; Bomel, Pierre; Senn, Eric; Martin, Éric

doi:10.1109/iscas.2005.1464679

Cited by 11 publications

(4 citation statements)

References 8 publications

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“…The mandatory constraints are the throughput (specified through an Initiation Interval II which represents the constant interval between the start of successive iterations) and the clock period. Optional design constraints are memory mapping [9] and 110 timing diagram [10] [11].…”

Section: Gautoverviewmentioning

confidence: 99%

High-Level Synthesis: On the path to ESL design

Coussy

Heller

2011

2011 9th IEEE International Conference on ASIC

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In the SoCs context, the traditional IC design methodology relying on EDA tools used in a two stages design flow (a VHDLNerilog RTL specification, followed by logical and physical synthesis) is no more suitable. Designing MPSoC requires new design approaches raising the specification abstraction up to Electronic System Level (ESL). Hence, virtual prototyping, design space exploration and high-level/system synthesis with the goal of optimised and functionally correct product implementation are needed. In this paper, we present the High-Level Synthesis (HLS) tool named GAUT. From a bit-accurate C/C++ specification and a set of design constraints, GAUT automatically generates a potentially pipelined RTL architecture described in both VHDL and SystemC respectively used for synthesis and virtual prototyping. Results demonstrate the interest of the tool on a MJPEG application and its capability in exploring various SoC design tradeoffs including several hardware accelerators HW-ACCs.

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Section: Gautoverviewmentioning

confidence: 99%

High-Level Synthesis: On the path to ESL design

Coussy

Heller

2011

2011 9th IEEE International Conference on ASIC

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“…Numerous academic tools and commercial products have also been developed. On the commercial side, we found products such as CATAPULT C 2 and CODEVELOPER 3 , while on the academic front, tools such as SPARK [16] and GAUT [17] are available. The drawback related to these tools is mainly that they are usually text based in nature making system hierarchy difficult to visualize and they are normally non-compatible.…”

Section: Related Workmentioning

confidence: 99%

Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation

Quadri

Meftali

Dekeyser

2010

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)

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Abstract-Due to continuous hardware/software evolution related to Systems-on-Chip (SoC) and the addition of features such as Partial Dynamic Reconfiguration, the complexity of SoC design and development has escalated exponentially. This has resulted in increased time to market and development costs. Without the usage of effective design tools and methodologies, large complex SoCs are becoming increasingly difficult to manage, resulting in a productivity gap. The design space, representing all technical decisions that need to be elaborated by the SoC design team is therefore, becoming immense and difficult to explore. Similarly, manipulation of these systems at low implementation levels such as Register Transfer Level (RTL) can be hindered by human interventions and the subsequent errors. This paper presents a novel design methodology that decreases the design complexity by raising the design abstraction levels. It makes use of ModelDriven Engineering and the UML MARTE profile to move from high level UML models to automatic code generation, for implementing dynamically reconfigurable SoCs.

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“…In more general terms FGDRA can achieve much better efficiency than GPP does, while offering the same versatility and, potentially, a very close flexibility. The counterpart is that 1 Fine Grained Dynamically Reconfigurable Architecture 2 Operating system enabled Low LAtency Fgdra 3 Reconfigurable System on Chip Fig. 1.…”

Section: Introductionmentioning

confidence: 99%

“…First by providing powerful CAD tool. Lots of research are thus led in the field of high level synthesis [1]. The second way is to abstract the system complexity by providing a middle layer, e.g an operating system, that abstracts the lower level of the system [2].…”

Section: Introductionmentioning

confidence: 99%

OLLAF : A dual plane reconfigurable architecture for OS support

Garcia

Granado

2008

2008 3rd International Design and Test Workshop

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In the context of large versatile platform for embedded real time system on chip, a fine grained dynamically reconfigurable architecture could be used as one possible computational resource. In order to manage efficiently this resource we need a specific OS kernel able to manage such a hardware adaptable architecture. Both the history of microprocessor based system and our previous work based on currently available FPGA devices led us to think that not only an OS kernel must be defined to handle an FGDRA 1 but a FGDRA must also be designed to handle this OS kernel. This article relate our original work in this direction. OLLAF 2 , an original FGDRA core that we have designed will be presented. A comparison with other methods used today using commercially available FPGA is also presented concerning the particular preemption service.

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High-level synthesis under I/O Timing and Memory constraints

Cited by 11 publications

References 8 publications

High-Level Synthesis: On the path to ESL design

High-Level Synthesis: On the path to ESL design

Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation

OLLAF : A dual plane reconfigurable architecture for OS support

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