High mobility MISFET with low trapped charge in HfSiO films

Morioka, A.; Watanabe, H.; Miyamura, Miharu; Tatsumi, T.; Saitoh, Motofumi; Ogura, Takashi; Iwamoto, Toshiyuki; Ikarashi, Taeko; Saito, Y.; Okada, Yoshitaka; Mochiduki, Yuuki; Mogami, Tohru

doi:10.1109/vlsit.2003.1221137

Cited by 38 publications

(26 citation statements)

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“…While significant progress has been made in fabricating high-κ gate stacks with less charge trapping [66][67][68][69], pulse-based characterization techniques [30,[70][71][72][73] remain critically important in understanding charge trapping processes for low power applications, memory cells, etc. This review addresses pulsed currentvoltage (I-V) characterization and analysis approaches.…”

Section: Introductionmentioning

confidence: 99%

The Pulsed I_d-V_gmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

Young¹,

Heh

Choi

et al. 2010

JSTS:Journal of Semiconductor Technology and Science

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Section: Introductionmentioning

confidence: 99%

The Pulsed I_d-V_gmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

Young¹,

Heh

Choi

et al. 2010

JSTS:Journal of Semiconductor Technology and Science

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“…Even with the metal sputtering process, our metal/HfSiO stack shows a lower Jg than poly-Si/HfSiO(N) samples due to the absence of poly-Si deposition and activation annealing, which probably produces defects at the poly-Si/HfSiO(N) interface: the former showed two orders of magnitude smaller leakage than the poly-Si/HfSiO(N) transistors under accumulation bias (data not shown). 11) Of course, elimination of poly-Si depletion also plays a key role in enhancing the figure of merit for leakage reduction under transistor operation. The overall leakage reduction of six orders of magnitude was a consequence of these two contributions.…”

Section: Resultsmentioning

confidence: 99%

“…Using our HfSiO, we have obtained over 95% carrier mobility for poly-Si gate transistors at 0.8 MV/ cm compared with the poly-Si/SiO 2 transistors. 11) Gate metal materials were selected by considering their WF values. We consider that suitable WF's should be near 4.9 eV for PMOS devices and 4.3 eV for NMOS devices to set the Vth in the range form 0.3 V to 0.5 V at a channel doping of approximately 1 Â 10 18 cm À3 (Channel doping much higher than 1 Â 10 18 cm À3 causes mobility degradation and increasing gate-induced drain leakage (GIDL), and the short-channel effect and Vth instability are caused at much lower channel doping).…”

Section: Methodsmentioning

confidence: 99%

Collective modes in coupled unstable resonators

Elkin¹,

Korotkov²,

Likhanskiǐ³

et al. 1989

Sov. J. Quantum Electron.

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Dual metal gate transistors with high-k gate dielectrics have been investigated for low-power metal oxide semiconductor (MOS) devices in 45 nm nodes and beyond. Using high-quality HfSiO gate dielectrics, using TiN and Ta for the gate electrode, and minimizing process damage, we have succeeded in markedly improving device performance. Effective work functions of 4.9 eV for TiN and 4.3 eV for Ta on HfSiO were obtained for the first time. Symmetrical threshold voltages of AE0:5 V were realized for these work functions. Small hysteresis and low interface trap densities for both TiN and Ta were obtained, which are almost the same as those of poly-Si/HfSiON transistors. No degradation in electron mobility was achieved for the first time for Ta-NMOS transistors at an effective field of 1.0 MV/cm. The gate leakage current at an equivalent electrical oxide thickness in an inversion of 1.7 nm was suppressed to 1 mA/cm À2 at a gate bias of Vth þ 0:6 V.

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“…On the other hand, many problems with the Hf-based gate dielectric have been reported, for example, Fermi-level pinning [9], mobility degradation, larger flicker noise [10], and lower reliability [11], compared to the conventional SiON. Recently, the methods to Manuscript [13] and to improve the mobility [14] have been shown. However, a transistor with high-k is still under investigation.…”

Section: Introductionmentioning

confidence: 99%

Highly Manufacturable and Reliable HfSiON N-FET With Poly-Si/a-Si Stacked Gate for LSTP Applications

Yasuda

Yamamoto

Yamagata

et al. 2008

IEEE Trans. Semicond. Manufact.

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We have proposed a novel poly-Si/a-Si/HfSiON transistor to enhance reliabilities without performance degradation for a 65-nm-node low standby power (LSTP) application. By insertion of a thin amorphous-Si layer between the Poly-Si gate electrode and HfSiON, both phosphorus penetration from gate electrode and a reaction at gate electrode/HfSiON interface are successfully suppressed, so that positive bias temperature instability, one of the biggest issues for high-k gate dielectric, is drastically improved by two orders of magnitude.By carefully optimizing the gate stack structure of HfSiON, the HfSiON device can satisfy both lower gate leakage and gate-induced drain leakage at the same time. As a result, an excellent I on I standby (= I g + I o ) characteristic can be achieved, compared to the conventional SiON device.The a-Si insertion technique can realize the combination between the high-k gate dielectric and Poly-Si for future LSTP applications.Index Terms-Amorphous-Si (a-Si), gate leakage, gate-induced drain leakage (GIDL), HfSiON, high-k, phosphorus, positive bias temperature instability (PBTI), reliability.

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High mobility MISFET with low trapped charge in HfSiO films

Cited by 38 publications

References 1 publication

The Pulsed I_d-V_gmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

The Pulsed I_d-V_gmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

Collective modes in coupled unstable resonators

Highly Manufacturable and Reliable HfSiON N-FET With Poly-Si/a-Si Stacked Gate for LSTP Applications

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High mobility MISFET with low trapped charge in HfSiO films

Cited by 38 publications

References 1 publication

The Pulsed Id-Vgmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

The Pulsed Id-Vgmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

Collective modes in coupled unstable resonators

Highly Manufacturable and Reliable HfSiON N-FET With Poly-Si/a-Si Stacked Gate for LSTP Applications

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The Pulsed I_d-V_gmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

The Pulsed I_d-V_gmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics