We report on atomic layer deposited Hf0.5Zr0.5O2 (HZO)-based capacitors which exhibit excellent ferroelectric (FE) characteristics featuring a large switching polarization (45 μC/cm2) and a low FE saturation voltage (∼1.5 V) as extracted from pulse write/read measurements. The large FE polarization in HZO is achieved by the formation of a non-centrosymmetric orthorhombic phase, which is enabled by the TiN top electrode (TE) having a thickness of at least 90 nm. The TiN films are deposited at room temperature and annealed at 400 °C in an inert environment for at least 1 min in a rapid thermal annealing system. The room-temperature deposited TiN TE acts as a tensile stressor on the HZO film during the annealing process. The stress-inducing TiN TE is shown to inhibit the formation of the monoclinic phase during HZO crystallization, forming an orthorhombic phase that generates a large FE polarization, even at low process temperatures.

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We report on the effect of the Hf0.5Zr0.5O2 (HZO) film thickness on the ferroelectric and dielectric properties using pulse write/read measurements. HZO films of thicknesses ranging from 5 to 20 nm were annealed at 400 °C for 1 min in a nitrogen ambient to be compatible with the back-end of the line thermal budget. As the HZO film thickness decreases, low-voltage operation (1.0 V or less) can be achieved without the dead layer effect, although switching polarization (Psw) tends to decrease due to the smaller grain size. Meanwhile, for 20-nm-thick HZO films prepared under the identical stress (similar TiN top electrode thickness and thermal budget), the Psw and dielectric constant are reduced because of additional monoclinic phase formation.

Transition metal dichalcogenides (TMDs) have attracted intensive attention due to their atomic layer-by-layer structure and moderate energy bandgap. However, top-gated transistors were only reported in a limited number of research works, especially transistors with a high-k gate dielectric that are thinner than 10 nm because high-k dielectrics are difficult to deposit on the inert surface of the sulfide-based TMDs. In this work, the authors fabricated and characterized top-gated, few-layer MoS2 transistors with an 8 nm HfO2 gate dielectric. The authors show that the cleaning effect of ultrahigh vacuum annealing before high-k deposition results in significantly reduced gate leakage current of HfO2, and they show that N2 or a forming gas anneal after device fabrication affects the threshold voltage, drive current, dielectric leakage, and C-V frequency dependence. This work demonstrates how the fabrication process can affect the yield and the electrical characterization of top-gated TMD transistors, which in effect can help researchers further enhance the performance of their devices.

In this letter, the ferroelectric (FE) properties of 5-nm-thick Hf0.5Zr0.5O2 (HZO) films deposited by atomic layer deposition have been investigated. By reducing the HZO film thickness to 5 nm, low-voltage operation (1.0 V) of the HZO-based capacitor was achieved while maintaining a remnant polarization (Pr) of about 10 μC/cm2 (i.e., 2Pr of 20 μC/cm2). Meanwhile, in order to form an orthorhombic phase, which is responsible for FE properties, a rapid thermal annealing process was performed after TiN top electrode deposition. The FE properties were realized after low temperature annealing (450 °C for 1 min), making them compatible with the back-end of the line. In addition, the low operating voltage and the suppression of an additional monoclinic phase formation by stress-induced crystallization induced a robust endurance (>1010 cycles at 1.2 V) of the 5-nm-thick HZO sample.