2012 International Electron Devices Meeting 2012
DOI: 10.1109/iedm.2012.6479070
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High on/off-ratio P-type oxide-based transistors integrated onto Cu-interconnects for on-chip high/low voltage-bridging BEOL-CMOS I/Os

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Cited by 11 publications
(5 citation statements)
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“…2. [10][11][12][13][14][15] As written in the conference proceeding, ability of high voltage operation with small feature size is expected as an interface bridge for signal conversion between CMOS core-logics with lowvoltages and peripheral devices driven with high-voltages. A p-type amorphous SnO TFT is developed as a complement component to n-type IGZO TFTs.…”
Section: Power Devicesmentioning
confidence: 99%
See 1 more Smart Citation
“…2. [10][11][12][13][14][15] As written in the conference proceeding, ability of high voltage operation with small feature size is expected as an interface bridge for signal conversion between CMOS core-logics with lowvoltages and peripheral devices driven with high-voltages. A p-type amorphous SnO TFT is developed as a complement component to n-type IGZO TFTs.…”
Section: Power Devicesmentioning
confidence: 99%
“…2. (Color online) BEOL transistor with an n-type IGZO film and ptype SnO film for on-chip high voltage I/Os in standard CMOS LSIs 13).…”
mentioning
confidence: 99%
“…Indeed, the integration of several memory circuits on top of CMOS logic circuit has been demonstrated with the improvement in terms of speed, power, and performance . This monolithic heterogeneous integration, however, requires a low-temperature process (≤400 °C) because (i) a high temperature negatively affects the performance of underlying CMOS logic devices and (ii) 3D stacking of nonvolatile memory, selector, and driver array favors the low-temperature process. , The p-type oxide semiconductor as well as n-type IGZO can be used as the essential ingredient for the memory selector and driver due to their low-temperature compatibility and good processability. , However, in the case of p-type oxide semiconductors, the valence band (VB) edge acts as a hole conduction path that is mainly formed of anisotropic and localized oxygen 2p orbitals, thereby resulting in a large hole effective mass ( m h *) and poor transport characteristics. Moreover, the p-type dopability is limited by the high formation energy of point defects, such as cation vacancies, that create free holes.…”
Section: Introductionmentioning
confidence: 99%
“…This shortcoming hinders the development of OS-based CMOS circuits. [10][11][12] To address this issue, several potential materials for realizing p-type devices, such as Cu 2 O, 13,14) Ag 2 O, 15,16) and SnO, [17][18][19][20] have been actively studied. Among them, SnO is the most attractive as its superior hole mobility performance has been demonstrated.…”
Section: Introductionmentioning
confidence: 99%