High Order Mismatch Shaping for Low Oversampling Rates

Abstract

Delta Sigma data converters employing high order dynamic element matching (DEM) allow for accurate signal conversion in the presence of DAC mismatch. However, at low oversampling rates, current high order DEM decoders provide little or no improvement in error suppression over lower order designs. In addition, the logic requirement of the DEM decoder increases significantly with each additional DAC bit. This paper presents a high order DEM decoder that improves mismatch shaping performance at low to medium oversampling rates by up to 15dB, while employing methods to reduce the area overhead of the vector quantizer in the design.

A Small‐Area, Low‐Power Delta‐Sigma DAC Applied to a Power‐Specific Chip

“…That is, the low-frequency adaptation error is pushed to the high frequency. In addition to the first-order error shaping algorithm, many researchers have proposed second-order or even higher-order shaping algorithms, such as vector-based error shaping [12][13][14] and tree structurebased error high-order shaping [15]. Owing to its complicated circuit structure and stability issues, high-order shaping is not taken into our consideration, although it has a better noise shaping performance than the first-order one.…”