High-order stitching overlay analysis for advanced process control

Systematic experimental study on stitching techniques of CMOS image sensors

“…The measurement of overlay pattern was used to define the stitched overlay and the details will be discussed in the next section. On the basis of experiment results [11], we have established a methodology for layout decomposition and guideline of the stitching for different layers. Without …”

“…In particular, we established an evaluation procedure to identify the baseline accuracy of different exposure tools, as well as the fundamental guarantee of the stitching techniques. Then, based on a series of experiments and analysis [9,10], a stitching overlay control approach using correctables generated from the overlay metrology system effectively reduce the distortion [11]. Finally, the proposed sensor is successfully implemented in a 0.055 µm CMOS process, which demonstrated on 12 inch silicon wafer.…”

A synchronous driving approach based on adaptive delay phase-locked loop for stitching CMOS image sensor

“…Thanks to the great development of CMOS stitching technology, it provides manufacturing guarantee for the research, design and implementation of super large array CMOS image sensor [6,7,8,9]. With the increase of the sensor array size, the length of the row line and the column line through the area array increases, which makes the parasitic parameters of the line increase sharply, resulting in serious challenges to the driving of row line and the read-out time of column line [10,11].…”