High performance 0.25 μm SRAM technology with tungsten interpoly plug

Abstract

A high performance 0.25pm CMOS process has been developed for fast static RAMS, featuring retrograde wells, shallow trench isolation with 0.55pm active pitch, a 55A nitrided gate oxide, 0.25pm polycide gate surface channel NMOS and PMOS transistors with drive currents of 630 and 300 pNpm respectively at an off-leakage of 10 pNpm, overgated TFTs with an odoff ratio greater than 6.1 05, stacked capacitors for improved SER, five levels of polysilicon planarized by chemicalmechanical polishing (CMP), with two self-aligned interpoly contacts and a tungsten interpoly plug (WIP) that connects 3 poly layers without parasitic diodes, 0.35 pm contacts and a 0.625pm metal pitch. A split word-line bitcell was scaled to an area of 3.74pm2 using 0.25pm design rules.

Silicon bipolar transistor scaling for advanced BiCMOS SRAM applications

“…The silicon bipolar transistors described in this paper are used for development of a O.25jim, 2.5V generation of BiCMOS SRAM technology [1]. This technology utilizes shallow trench isolation [2], triple poly layer and double metal process.…”