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A reliable metal-insulator-metal (MIM) capacitor exceeding 250nF has been integrated into the copper/low-K backend of a high-performance 90nm SOI technology. The reduction of supply grid voltage transients has enhanced microprocessor performance by approximately 10% without increasing the chip area or power consumption.

Trench dislocations in a 0.25um BiCMOS SRAM technology were traced to defects arising during S / D processing. It is argued that these defects coalesce to form dislocations, typically near the trench edge, under the combined influence of mechanical stress and high temperature processing. Process variables impacting the generation of these dislocations, including layout geometry; trench depth, profile, and densification; the presence of a liner under the gate spacer nitride; and S / D implant condition and anneal are studied. Based on this analysis, a defect-free BiCMOS process is proposed. It is shown that although the incidence of trench dislocations could be decreased by reducing the overall stress in the flow, eliminating Sill implant defects is the key to completely removing the trench dislocations.Controlling process-induced stress is an increasing concem with each succeeding generation of IC process. Increasing packing density and reducing feature size lead to higher wafer stress levels [I]. With the drive toward low thermal budget processing, the ability of materials to relieve stress by flow processes decreases as well. A number of recent publications have discussed silicon dislocations observed with the introduction of shallow trench isolation [2-41. These papers have invoked mechanical stress as the primary cause of these dislocations and have identified methods to reduce stress in the silicon to eliminate these dislocations. However, they do not clearly identify the process step which is the source of these dislocations and reducing the stress alone does not always eliminate the defects completely. In this work, we demonstrate that point defects generated during heavy sourcddrain implantation form the nuclei for trench dislocations, which under the combined influence of mechanical stress and high temperature processing typically glide to the region of maximum stress.We also propose a defect free solution based on annealing the implant damage to ensure that any subsequent changes in the process or the layout do not regenerate these dislocations.Description of Defects This work was based on a 0.25pm BiCMOS SRAM technology with shallow trench isolation which was reported previously [51. This triple poly/triple metal BiCMOS SRAM process consisted of buried layer and epitaxy followed by shallow trench isolation. The active pattern was defined using DUV lithography and etched to create 3500A deep trenches. The trenches were filled with 0,-TEOS and annealed at high temperature prior to trench CMP. The gate stack consisted of poly-Si /Wsi,/ Si,N, cap with Si,N, spacers. Heavy dose arsenic n+ sourcddrain implants were followed by a poly-2 self-aligned contact formation. Poly-3 load resistor and backend processing for the contacts and metal layers completed the process. Figure 1 is a E M cross-section of this technology.Trench dislocations were observed in the memory array of this 0.25um 1Mb SRAM at the end of line. These dislocations were typically initiated near the bottom comer of the trench, terminating eith...

It is shown that fluorine plays a major role in the penetration of boron into and through the gate oxides of P·channel MOSFETs which employ P+ doped polysilicon gates. Boron penetration results in large positive shifts in V F B, increased P-channel subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. 'Inclusion of a phosphorus co·implant or TiSi2 salicide is shown to minimize this effect. The boron penetration phenomenon is modeled by the creation of a very shallow, fully·depleted P·type layer in the silicon substrate close to the Si02/Si interface. Elemental boron is shown to be superior to B F2 as an implant species for surface channel submicron PMOS devices.

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