High-Performance 1-Bit Full Adder With Excellent Driving Capability for Multistage Structures

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Sophisticated systems take advantage of approximate circuits for energy management. A gate-level structure is introduced to make a novel imprecise full adder (FA) cell by the gate diffusion input (GDI) strategy. The carbon nanotube field-effect transistor (CNTFET) technology lowers the FA power, and the swing issue is resolved by the dynamic threshold (DT) technique. The FA specifications are 10 transistors, two internal nodes, 0.191-μm 2 area, three errors, and an error rate (ER) of 37.5%. Some inputs are directly passed to the final stage of the FA to reduce the delay and dynamic power. The FA is used in three 4:2 compressors with 12, 16, and 20 transistors, respectively. The compressors are based on the modified stacking concept to attain low power, small area, and high speed. The compressors are used up in the partial product reduction tree (PPRT) of a new 8-bit inexact multiplier. Regarding the multiplier, the power-delay product (PDP) is decreased by 25.21%, and the normalized mean error distance (NMED) shows high accuracy. An imprecise discrete cosine transform (DCT) is implemented by the multiplier for image compression, and compared with the literature, the peak signal-to-noise ratio (PSNR) and structural similarity index metric (SSIM) are amended by 8.26% and 7.29%, respectively.

Section: Imprecise Fa Cellmentioning

confidence: 99%

Section: Presented High-efficient Inexact Multipliermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A high‐efficient imprecise discrete cosine transform block based on a novel full adder and Wallace multiplier for bioimages compression

Esmaeili

Pesaran

Shiri

2023

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“…However, ( 13) is used to complete (12), which also includes the number of used transistors as area occupation of the cells.…”

Section: Case Study: Image Processing Using Single-bit Comparatorsmentioning

confidence: 99%

“…Importance and optimizations of parameters including switching time, drive capability, and input capacitance address efficient digital circuits. 11 CMOS digital circuits are reliable, low-power, and full-swing, 12 but in the complicated circuits, the high number of internal nodes and transistors, direct paths from the power supply (V DD ) to the ground (GND), and long signal paths from inputs to outputs increase the delay, power, and area. 10 A 1-bit comparator designed in Cheng 13 (CMOS-1) which composed of two inverters, two AND gates, and a NOR gate as shown in Figure 2A.…”

Section: Introductionmentioning

confidence: 99%

SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits

Shiri

Sadeghi

Rafiee

et al. 2022

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Summary The performance of the programmable integrated circuits (ICs) like digital signal processors (DSPs), central processing units (CPUs), and microcontrollers is highly dependent on the magnitude comparators. This article presents a new reliable and efficient 1‐bit comparator based on carbon nanotube field‐effect transistors (CNTFETs) technology. The gate diffusion input (GDI) technique is used to reduce the number of transistors. Also, single swing restoration (SR) transistors and transmission gate (TG) techniques are combined to attain full‐swing outputs with high driving capability. The low internal capacitances and the fewer number of internal nodes of the proposed comparator make it low‐power both in single‐bit and multibit (2‐bit, 4‐bit, 8‐bit, and 16‐bit) implementations. Variations analyses of the circuit and technology parameters are performed that show the cell efficiency. From the layout results, the 1‐bit and 16‐bit comparators occupy 0.1944 μm2 and 37.485 μm2 as the total die area, respectively. The proposed circuit is implemented in image processing in which the best performance compared with state‐of‐the‐art designs regarding hardware complexity, circuitry performance, and image quality assessments are confirmed, by at least 50% improvements of different critical parameters. The resulted figure of merits nominates the cell for future ICs.

A new ripple carry adder structure based on a swing‐boosted full adder for concurrent error correction in low‐resolution pipeline analog‐to‐digital converters

Tahghigh,

Shiri

2024

SummaryA ripple carry adder (RCA) structure is presented which can concurrently correct a gain error in low‐resolution pipeline analog‐to‐digital converters (ADCs). The RCA is composed of a new swing‐boosted full adder (FA) based on the transmission gate (TG) technique. So, it is low‐power, high‐speed, and full‐swing with high driving capability. In 90 nm technology, the results of power, delay, and power‐delay‐product (PDP) of the FA are 1.5296 μW, 2.1141 ns, and 3.2337 fJ, respectively. The RCA with an area of 408.09 μm2 is evaluated by a 3‐bit pipeline ADC with 1.5‐bit per stage. When the erroneous codes are passed through the RCA, the maximum and minimum integral nonlinearity (INL) are improved by 19.83% and 90.98%, while the maximum and minimum of the differential nonlinearity (DNL) are improved by 50%, and 42.06%, respectively.