High performance 300mm backside illumination technology for continuous pixel shrinkage

Yaung, Dun–Nian; Hsieh, B. C.; Wang, C.C.; Liu, J.C.; Wang, T.J.; Wang, W.D.; Chuang, Chia-Wei; Chao, Calvin Yi‐Ping; Tu, Y. L.; Tsai, C.S.; Hsu, Tsun-Lai; Ramberg, F.; Mo, Wenxiong; Rhodes, H.; Tai, Derrick; Venezia, V. C.; Wuu, Shou-Gwo

doi:10.1109/iedm.2011.6131512

Cited by 14 publications

(4 citation statements)

References 4 publications

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“…Backside illumination technology has been developed and has enabled drastic S/N improvement [ 5 , 6 ]. Stacked CMOS image sensor (CIS) chips enable a more flexible manufacturing process dedicated to image sensors [ 7 ].…”

Section: Introductionmentioning

confidence: 99%

A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel

Takahashi

Huang

Sze

et al. 2017

Sensors

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A submicron pixel’s light and dark performance were studied by experiment and simulation. An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is promising in that it may enhance performance. In this work, we demonstrated a low dark current of 3.2 e−/s at 60 °C, an ultra-low read noise of 0.90 e−·rms, a high full well capacity (FWC) of 4100 e−, and blooming of 0.5% in 0.9 μm pixels with a pixel supply voltage of 2.8 V. In addition, the simulation study result of 0.8 μm pixels is discussed.

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Section: Introductionmentioning

confidence: 99%

A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel

Takahashi

Huang

Sze

et al. 2017

Sensors

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“…The top-tier wafer is thinned down to the target thickness, less than 3 µm, which is a very challenging task for 300 mm bulk silicon wafer based technology. The process includes chemical and mechanical etching, whereas epi-wafer quality and thin-down flow have been optimized, with a final thickness tolerance of less than 3% [9]. In addition, the defects induced by etching, which can degrade and even suppress SPAD operation, have been reduced by more than 10 times with this optimization process.…”

Section: Back-illuminated 3d-stacked Spadmentioning

confidence: 99%

“…In addition, a DCR of 55.4 cps/µm 2 and a jitter of 107 ps full width at half maximum (FWHM) at 2.5 V excess bias voltage are achieved, the lowest ever reported in a backilluminated 3D-stacked CMOS technology. This performance was reached through optimized 3D-stacking, with a tight control of damage, improved doping profiles, and an especially designed optical stack [9]- [11]. This performance was achieved through careful analysis of the devices via extensive TCAD [5] and JSSC'15 [6], (b) IEDM'16 [7].…”

Section: Introductionmentioning

confidence: 99%

High-Performance Back-Illuminated Three-Dimensional Stacked Single-Photon Avalanche Diode Implemented in 45-nm CMOS Technology

Lee

Ximenes

Parameswaran

et al. 2018

IEEE J. Select. Topics Quantum Electron.

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We present a high-performance back-illuminated three-dimensional stacked single-photon avalanche diode (SPAD), which is implemented in 45-nm CMOS technology for the first time. The SPAD is based on a P + /Deep N-well junction with a circular shape, for which N-well is intentionally excluded to achieve a wide depletion region, thus enabling lower tunneling noise and better timing jitter as well as a higher photon detection efficiency and a wider spectrum. In order to prevent premature edge breakdown, a P-type guard ring is formed at the edge of the junction, and it is optimized to achieve a wider photon-sensitive area. In addition, metal-1 is used as a light reflector to improve the detection efficiency further in backside illumination. With the optimized 3-D stacked 45-nm CMOS technology for back-illuminated image sensors, the proposed SPAD achieves a dark count rate of 55.4 cps/µm 2 and a photon detection probability of 31.8% at 600 nm and over 5% in the 420-920 nm wavelength range. The jitter is 107.7 ps full width at half-maximum with negligible exponential diffusion tail at 2.5 V excess bias voltage at room temperature. To the best of our knowledge, these are the best results ever reported for any back-illuminated 3-D stacked SPAD technologies.

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“…An example of an image from a scalable pixel direct bond BSI 3 Mpixel with 1.4 micron pixels CMOS image sensor, wafer bonded and thinned at Ziptronix and designed and tested at Silicon File is given in Figure 2. Pixel scaling down to 0.9 microns using 300mm direct wafer bonding has been demonstrated (22) and Sony has licensed direct bond technology for BSI applications from Ziptronix, Inc. (23).…”

Section: Backside Illuminated (Bsi) Cmos Image Sensorsmentioning

confidence: 99%

Applications Driving Adoption of Direct Bond Technology

Enquist¹

2012

ECS Trans.

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The high bond energy at low temperature capability of direct bond technology results in bonded structures and 3D ICs with the lowest distortion, highest density of 3D interconnects and thinnest form factor. These attributes and compatibility with industry standard manufacturing have led to the adoption of this technology in the supply chain for volume manufacturing of backside illuminated (BSI) image sensors. The establishment of this technology in the supply chain will reduce the adoption barrier for other applications including 3D BSI, RF front ends, 3D memory, and pico projectors.

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High performance 300mm backside illumination technology for continuous pixel shrinkage

Cited by 14 publications

References 4 publications

A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel

A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel

High-Performance Back-Illuminated Three-Dimensional Stacked Single-Photon Avalanche Diode Implemented in 45-nm CMOS Technology

Applications Driving Adoption of Direct Bond Technology

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