High Performance 65nm SOI Transistors Using Laser Spike Annealing

(Invited)Laser Annealing in CMOS Manufacturing

“…Figure 3. Arsenic SIMS profiles and corresponding sheet resistance for "RTA+LSA" annealing sequence (3). LSA recovers sheet resistance for low-temperature (LT) RTA.…”

“…The first applications for millisecond annealing were directed to improving dopant activation efficiency in the poly-silicon gate electrode and transistor source/drain (S/D) regions (3,4,5,11,12,13). Figure 2 shows a response of unsilicided-gate precision resistors to millisecond anneal temperature for both laser and flash lamp anneals with similar durations.…”

“…After decades of scientific inquiry (1,2), laser annealing was incorporated into CMOS manufacturing process at several fabrication facilities (FAB's) starting from the 65nm node in mid-2000s (3,4,5). Initial focus on nanosecond-scale laser melt annealing or Laser Thermal Processing (LTP) (6,7,8) did not gain any traction in CMOS fabrication due to a large surface temperature variability stemming from layoutdependent optical energy coupling into patterned substrates and transient heat transfer in microstructures with varying thermal properties.…”

Improved Frequency Response in a SiGe npn Device through Improved Dopant Activation

“…Laser or Flash annealing are used in advanced CMOS processing to activate dopants with minimum diffusion (8)(9). These techniques use msec timescales at temperatures that can approach the melting point of silicon.…”

Advanced Annealing Schemes for High-Performance SOI Logic Technologies

“…Rapid Thermal Processing and beyond: Applications in Semiconductor Processing In the literature (e.g. [10,11]) higher Ioff/Ion improvement in comparison to the reference technology was reported. As it is shown in Fig.…”