No abstract

Systematic studies of the heteroepitaxial growth of germanium nanowires on silicon substrates were performed. These studies included the effect of sample preparation, substrate orientation, preanneal, growth temperature, and germane partial pressure on the growth of epitaxial germanium nanowires. Scanning electron microscopy and transmission electron microscopy were used to analyze the resulting nanowire growth. Germanium nanowires grew predominantly along the ⟨111⟩ crystallographic direction, with a minority of wires growing along the ⟨110⟩ direction, irrespective of the underlying silicon substrate orientation [silicon (111), (110), and (100)]. Decreasing the partial pressure of germane increased the number of ⟨111⟩ nanowires normal to the silicon (111) surface, compared to the other three available ⟨111⟩ directions. The growth rate of nanowires increased with the partial pressure of germane and to a lesser degree with temperature. The nucleation density of nanowire growth and the degree of epitaxy both increased with temperature. However, increasing the growth temperature also increased the rate of sidewall deposition, thereby resulting in tapered nanowires. A two-step temperature process was used to initiate nanowire nucleation and epitaxy at a high temperature, followed by nontapered nanowire growth at a lower temperature. Preannealing gold films in hydrogen or argon before nanowire growth reduced the yield of nanowires grown on silicon samples, especially on silicon (111) substrates, but not on silicon oxide. Gold annealing studies performed to investigate this preanneal effect showed greater gold agglomeration on the silicon samples compared to silicon oxide. The results and conclusions obtained from these studies give a better understanding of the complex interdependencies of the parameters involved in the controlled heteroepitaxial growth of vapor-liquid-solid grown germanium nanowires.

Diffusion of oxygen ions in thin (≲40 Å) HfO2 gate dielectric films is measured using transient gate currents. The diffusion coefficient is estimated to be ∼1×10−14 cm2/s at room temperature, and is observed to be thermally activated with an activation energy of ∼0.52 eV for nanometer scale HfO2 films. The diffusion results are shown to be consistent with those for positively charged oxygen vacancies in bulk samples of similar oxides, and first principle calculation results for oxygen vacancy diffusion in thin HfO2 films. Thus, we demonstrate a method for measuring oxygen diffusion in thin HfO2 films where diffusion measurements by the conventional techniques have been elusive.

This paper summarizes studies performed using capping layers in conjunction with high-K dielectrics to obtain band-edge CMOS devices. MgO and Al2O3 cap layers are evaluated for nFET and pFET devices respectively. By precisely positioning the cap materials in the gate stack and evaluating their effect as a function of process temperature and capping layer thickness, a deeper understanding of the mechanism of threshold voltage shift caused by the capping layers is obtained. MgO is observed to readily diffuse into the HfO2 stack at temperatures as low as 600 oC while Al2O3 diffuses through HfO2 at higher temperatures of 1000 oC. MgO caps located below the HfO2 and processed at 600 oC provide the best scaling and maximum voltage shift, while a trade-off between scaling and voltage shift has to be made when using Al2O3 caps.

FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (R para ) degraded by 3-D structure with thin Si-body. The issue of V t -mismatch is discussed for continuous FinFET SRAM cell-size scaling.IEDM09-290 12.1.2