High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling

Bangsaruntip, Sarunya; Cohen, Guy; Majumdar, Amlan; Zhang, Y.; Engelmann, Sebastian; Fuller, N.; Gignac, Lynne; Mittal, S.; Newbury, J.; Guillorn, Michael A.; Barwicz, Tymon; Šekarić, L.; Frank, Martin M.; Sleight, J.W.

doi:10.1109/iedm.2009.5424364

Cited by 250 publications

(137 citation statements)

References 7 publications

Supporting

Mentioning

130

Contrasting

Unclassified

Order By: Relevance

“…Examples are 3-dimensional gate etch applications which demand essentially infinite etch selectivity while avoiding introduction of materials damage as FinFETs, Trigates, nanowires and other 3D devices are produced. [14][15][16] For these applications the top of the fin/wire is exposed to the plasma and needs to withstand plasma exposure while the remaining gate is formed around the fin/wire.…”

Section: Technology Demands On Plasma Etch (Pe) and Key Shortcomings mentioning

confidence: 99%

Atomic Layer Etching at the Tipping Point: An Overview

Oehrlein

Metzler

2015

ECS J. Solid State Sci. Technol.

232

162

View full text Add to dashboard Cite

The ability to achieve near-atomic precision in etching different materials when transferring lithographically defined templates is a requirement of increasing importance for nanoscale structure fabrication in the semiconductor and related industries. The use of ultra-thin gate dielectrics, ultra thin channels, and sub-20 nm film thicknesses in field effect transistors and other devices requires near-atomic scale etching control and selectivity. There is an emerging consensus that as critical dimensions approach the sub-10 nm scale, the need for an etching method corresponding to Atomic Layer Deposition (ALD), i.e. Atomic Layer Etching (ALE), has become essential, and that the more than 30-year quest to complement/replace continuous directional plasma etching (PE) methods for critical applications by a sequence of individual, self-limited surface reaction steps has reached a crucial stage. A key advantage of this approach relative to continuous PE is that it enables optimization of the individual steps with regard to reactant adsorption, self-limited etching, selectivity relative to other materials, and damage of critical surface layers. In this overview we present basic approaches to ALE of materials, discuss similarities/crucial differences relative to thermal and plasma-enhanced ALD, and then review selected results on ALE of materials aimed at pattern transfer. The overview concludes with a discussion of opportunities and challenges ahead. A requirement of increasing importance for nanoscale device fabrication is the ability to achieve atomic scale etching control and materials selectivity during pattern transfer.1-8 An etching method corresponding to Atomic Layer Deposition (ALD), i.e. Atomic Layer Etching (ALE), is expected to satisfy these needs as critical dimensions continue to shrink below the 10 nm scale.Demonstrations of self-limited dry etching methods capable of near-atomic resolution have a long history in the dry etching community and a brief review will be presented below. Key challenges for these approaches have been specialized equipment, long process times and low throughput.9,10 However, a recent demonstration using a commercial plasma etch tool 10 and activities within the dry etching community 11 provide indications that the situation has changed, and that we may have reached for ALE the Tipping Point which Gladwell defined as the "the moment of critical mass, the threshold, the boiling point" when "ideas and products and messages and behaviors spread like viruses do".12 This is due to several factors, including unprecedented demands on dry etching technology introduced by the semiconductor device evolution according to Moore's law that can be satisfied by atomic layer etching, advanced capabilities in plasma etch, and the existence of a critical level of information on plasma etch and ALD methods as applied in the semiconductor fabrication space.In this article we will provide a review of background of these approaches, and focus on issues that have to be overcome for widespread implement...

show abstract

Section: Technology Demands On Plasma Etch (Pe) and Key Shortcomings mentioning

confidence: 99%

Atomic Layer Etching at the Tipping Point: An Overview

Oehrlein

Metzler

2015

ECS J. Solid State Sci. Technol.

232

162

View full text Add to dashboard Cite

show abstract

“…On the other hand, fixed parameters do not play a significant role in the logic gate delay or reflect the process-dependent parts [9]. However, it should be noted that I ON (the drive current at V G =V D =V DD ) of FinFETs does not show a dramatic variation with the fluctuation of geometrical parameters, especially in the investigated range over H fin =20~60 nm and W fin =10~30 nm, while that of Si nanowire FETs with a surrounding gate is very sensitive to the variation of geometrical parameters [13]. [14] are satisfied as shown in Table 2, SCEs are efficiently suppressed in the simulation conditions.…”

Section: Design Parameter In Finfetsmentioning

confidence: 99%

Comparative Study on the Structural Dependence of Logic Gate Delays in Double-Gate and Triple-Gate FinFETs

Kim¹,

Jang²,

Yun³

et al. 2010

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness (T mask ) to the sidewall oxide thickness (T ox ) is T mask /T ox =10/2 nm for the minimum logic delay (τ) while T mask /T ox =5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length (L G ) and the fin width (W fin ) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized T mask /T ox , the propagation delay (τ) decreases with the increasing fin height H fin . It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as H fin increases. In the end, the sensitivity of Δτ/ΔH fin or ΔI ON '/ΔH fin decreases as L G /W fin is scaled-down.However, W fin should be carefully designed especially in circuits that are strongly influenced by the selfcapacitance or a physical layout because the scaling of W fin is followed by the increase of the selfcapacitance portion in the total load capacitance.

show abstract

“…The nanowires, FinFET, gate all around (GAA) has been the focus of consideration for the application of Microelectronics / Nanoelectronic engineering due to their short channel effects (SCE) and enhanced current capability in devices [8][9][10][11]. In this work an extended version of GAA has been analyzed.…”

Section: Introductionmentioning

confidence: 99%

Scaling Effect on Parameters of HfO2 Based CSDG MOSFET

Srivastava¹

2017

IJET

View full text Add to dashboard Cite

-To make obvious the advantages of Nanoelectronic circuits with addition of functionality and chip density compared to the simple switch, application of cylindrical surrounding double-gate (CSDG) MOSFET is suitable. In addition to the Silicon-dioxide, in this present work, a high dielectric material (HfO 2 ) has been added. Various parameters such as scaling of device, thermal effect, ON-resistance and capacitances, equivalent oxide thickness, capacitance equivalent thickness, and breakdown of a CSDG MOSFET has been discussed. This provides an improved MOSFET to drive the nanotechnology circuit with minimum signal propagation delay.

show abstract

High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling

Cited by 250 publications

References 7 publications

Atomic Layer Etching at the Tipping Point: An Overview

Atomic Layer Etching at the Tipping Point: An Overview

Comparative Study on the Structural Dependence of Logic Gate Delays in Double-Gate and Triple-Gate FinFETs

Scaling Effect on Parameters of HfO2 Based CSDG MOSFET

Contact Info

Product

Resources

About