High performance and low leakage current InGaAs-on-silicon FinFETs with 20 nm gate length

Sun, Xun; D’Emic, C.; Cheng, C.-W.; Majumdar, Amlan; Sun, Y.; Cartier, E.; Bruce, Robert L.; Frank, Martin M.; Miyazoe, Hiroyuki; Shiu, Kuen-Ting; Lee, Jangwook; Rozen, John; Patel, J.; Ando, Takashi; Song, Woo-Bin; Lofaro, M.; Krishnan, M.; Obrodovic, B.; Lee, K.-T.; Tsai, Hsinyu; Wang, W.-E.; Spratt, William; Chan, K.; Yau, Jeng-Bang; Hashemi, Pouya; Khojasteh, Mahmoud; Cantoro, Mirco; Ott, J. A.; Rakshit, Titash; Zhu, Yu; Sadana, D. K.; Yeh, Chun-Chen; Narayanan, V.; Mo, R.; Heo, Y.-C.; Kim, D.-W.; Rödder, M.; Leobandung, E.

doi:10.23919/vlsit.2017.7998193

Cited by 19 publications

(8 citation statements)

References 3 publications

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“…III-V materials [6], [7] are attractive in such systems, both as CMOS and RF performance boosters [8], [9] through high electron mobility, as well as enablers of new functionalities, e.g., as direct band gap materials. Hybrid solutions, combining Si CMOS and III-V channels [10], [11], furthermore, can leverage the low thermal budget process of III-V FETs [12], typically sub-600 • C, to avoid degradation of reliability and performance of the bottom level Si CMOS. We have previously demonstrated III-V InGaAs MOSFETs directly integrated on top of a pre-processed Si CMOS wafer [13]- [16], with InGaAs MOSFET performance approaching but not yet matching state-of-the-art InGaAs devices fabricated on silicon substrate [17]- [21], a challenging target due to the difference in fabrication complexity.…”

Section: Introductionmentioning

confidence: 99%

InGaAs FinFETs 3-D Sequentially Integrated on FDSOI Si CMOS With Record Performance

Convertino

Zota

Caimi

et al. 2019

IEEE J. Electron Devices Soc.

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In this paper, we demonstrate InGaAs FinFETs 3-D sequentially (3DS) integrated on top of a fully depleted silicon-on-insulator CMOS. Top layer III-V FETs are fabricated using a Si CMOS compatible HKMG replacement gate flow and self-aligned raised source-drain regrowth. We demonstrate that the low thermal budget of the top layer process does not affect the lower level FETs performance. An on-current of 200 μA/μm (at I OFF = 100 nA/μm and V DD = 0.5 V) is achieved, representing the highest reported for 3DS integrated III-V FETs on silicon, showing a 50% improvement in R ON compared to previous work. The achieved improved performance can be attributed to the introduction of spacers, doped extensions underneath the gate region as well as improvements in the direct wafer bonding technique.

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Section: Introductionmentioning

confidence: 99%

InGaAs FinFETs 3-D Sequentially Integrated on FDSOI Si CMOS With Record Performance

Convertino

Zota

Caimi

et al. 2019

IEEE J. Electron Devices Soc.

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“…Figs. 5a and b give the output conductance of two n-type devices (T 1 − T 2 ), which is plotted using (10). At every V gs and V ds value, the modelled characteristics are in a reasonable compliance with the experimental data, both in the linear and saturation region of operations.…”

Section: Resultsmentioning

confidence: 64%

“…It can be seen from the figure that the channel is completely covered by the gate of the device. This allows the gate 3D control on the channel and reduces the leakage current of the device to a significant level [10].…”

Section: Introductionmentioning

confidence: 99%

Non‐linear compact model for FinFETs output characteristics

Ahmed

Memon

2019

IET Circuits, Devices & Systems

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In this study, a non-linear compact model for I-V characteristics of FinFETs is presented. The model is developed using the profile of drifting carriers, which plays an important role in determining the device characteristics. A mobility model which incorporates the effect of applied potentials is developed and is used to predict the I-V response of the device. Particle swarm parameter extraction technique is engaged for optimum model applications. It is demonstrated by using the experimental data reported in the literature, that the proposed model can predict the I-V characteristics of FinFETs fabricated using Si and GaN materials having gate lengths ranging from 0.05 to 1 μm.

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“…In the post-Moore era, several alternative materials have been explored to continue the semiconductor roadmap. III-V compounds are of great interest due to their direct bandgap and high electron and hole mobilities [1]- [3]. Very recently, public attention shifted to two-dimensional materials [4]- [9], which have a stacked layer structure due to the van der Waals forces that bind the layer structure stably.…”

Section: Introductionmentioning

confidence: 99%

Contact Engineering of Trilayer Black Phosphorus With Scandium and Gold

Tsai

Magyari-Köpe

et al. 2019

IEEE J. Electron Devices Soc.

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High contact resistance keeps black phosphorus (BP) from fully wielding its excellent material property. Using first-principles calculations, we analyze the interfacial binding behavior and the impact of binding on the other layers of a trilayer BP. We found that the interfacial charge density and charge transfer of Scandium (Sc)-contacted trilayer BP are 2.67 and 3.29 times greater than Au-contacted trilayer BP, respectively. Moreover, the interfacial tunneling barrier height and width of Sc-contacted trilayer BP are 0 eV and 1.851 Å, which are significantly smaller than that of 5.1 eV and 2.447 Å observed in Au-contacted trilayer BP. All these facts suggest a strong bonding and efficient carrier transmission between Sc contact and trilayer BP substrate. Therefore, we conclude that the Sc electrode can lead to a superior performance that is consistent with the experiment.

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High performance and low leakage current InGaAs-on-silicon FinFETs with 20 nm gate length

Cited by 19 publications

References 3 publications

InGaAs FinFETs 3-D Sequentially Integrated on FDSOI Si CMOS With Record Performance

InGaAs FinFETs 3-D Sequentially Integrated on FDSOI Si CMOS With Record Performance

Non‐linear compact model for FinFETs output characteristics

Contact Engineering of Trilayer Black Phosphorus With Scandium and Gold

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