InGaAs FinFETs 3-D Sequentially Integrated on FDSOI Si CMOS With Record Performance

Convertino, Clarissa; Zota, Cezar B.; Caimi, Daniele; Sousa, Marilyne; Czornomaz, Lukas

doi:10.1109/jeds.2019.2928471

Cited by 14 publications

(6 citation statements)

References 23 publications

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“…Note that the ION/IOFF ratio of the DG-UTB device under study is about 4 orders of magnitude (see Fig. 4), which is in line with ITRS requirements [12] as well as state-of-the-art InGaAs Tri-Gate devices on Si-substrates [27], with record value as high as ~2000-2500 (for LG as low as 13 nm). These remarks demonstrate that although the DG-UTB device in this work represents a simplified version of realistic technology, the variability analysis carried out can be considered to be relevant for current state-of-the-art InGaAs devices.…”

Section: Calibration Of Quantum Drift-diffusion Simulationssupporting

confidence: 82%

“…b), c) show the trapped charge density (NTRAP) and electron mobility (μn) vs the inversion charge density (NINV) with the two trap distribution [black solid (blue dashed) curve in a) used in the MSMC w/ WFP (w/o WFP)], showing that the proposed approach does not modify the electrostatic and transport behavior of the device even when the WFP in the gate oxide is not accounted for. realizations include a thin Al2O3 interfacial layer (~5-10 Å) between HfO2 and the semiconductor [27]. The geometrical parameters are reported in the caption of Fig.…”

Section: Multi-subband Monte Carlo Modelingmentioning

confidence: 99%

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Systematic Modeling of Electrostatics, Transport, and Statistical Variability Effects of Interface Traps in End-of-the-Roadmap III–V MOSFETs

Zagni

Caruso

Puglisi

et al. 2020

IEEE Trans. Electron Devices

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Thanks to their superior transport properties, Indium Gallium Arsenide (InGaAs) Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) constitute an alternative to conventional Silicon MOSFETs for digital applications at ultrascaled nodes. The successful integration of this technology is challenged mainly by the high defect density in the gate oxide and at the interface with the semiconductor channel, which degrades the electrostatics and could limit the potential benefits over Si. In this work, we i) establish a systematic modeling approach to evaluate the performance degradation due to interface traps in terms of electrostatics and transport of InGaAs Dual-Gate Ultra-Thin Body (DG-UTB) FETs, and ii) investigate the effects of random interface-trap concentration as another roadblock to the scaling of the technology, due to statistical variability of the threshold voltage. Variability is assessed with a Technology CAD (TCAD) simulator calibrated against Multi-Subband Monte Carlo (MSMC) simulations. The modeling approach overcomes the TCAD limitations when dealing with ultra-thin channels (i.e., below 5 nm) without altering crucial geometrical parameters that would compromise the dependability of the variability analysis. Our results indicate that interface-trap fluctuation becomes comparable with the other variability sources dominating the total variability when shrinking the device dimensions, thus contrasting the trend of reduced variability with scaling. This in turn implies that interface and border traps may strongly limit the benefits of InGaAs over Silicon if not effectively reduced by gate process optimization.

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Section: Calibration Of Quantum Drift-diffusion Simulationssupporting

confidence: 82%

Section: Multi-subband Monte Carlo Modelingmentioning

confidence: 99%

Systematic Modeling of Electrostatics, Transport, and Statistical Variability Effects of Interface Traps in End-of-the-Roadmap III–V MOSFETs

Zagni

Caruso

Puglisi

et al. 2020

IEEE Trans. Electron Devices

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“…Combining the best of both the III-V and silicon CMOS world will lead to novel and better performing devices (higher speed and lower power consumption) and circuits, especially in the field of Radio/Frequency (RF) 1,2 and photonic applications. 3,4 The monolithic integration can be achieved by the hetero-epitaxial deposition of III-V materials on a silicon substrate.…”

mentioning

confidence: 99%

Electrical Activity of Extended Defects in Relaxed In_xGa_1−xAs Hetero-Epitaxial Layers

Claeys¹,

Hsu²,

Mols³

et al. 2020

ECS J. Solid State Sci. Technol.

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The electrical activity of extended defects in III–V materials, combining different analysis methods based on lifetime extraction from diode current-voltage characteristics, time resolved photoluminescence (TRPL) and deep level studies using Deep Level Transient Spectroscopy (DLTS) is reviewed. To that purpose p+n junction diodes have been fabricated in In0.53Ga0.47As hetero-epitaxial layers on semi-insulating InP or GaAs substrates. By depositing a strained buffer layer, the Extended Defect Density (EDD) can be varied over several decades, enabling a systematic study of their electrical impact in the same range. The defect densities are determined by High-Resolution X-ray Diffraction (HR-XRD), DLTS and Electron Channeling Contrast (ECCI) techniques. The generation and recombination (GR) lifetimes of the In0.53Ga0.47As layers become dominated by the EDs for densities above about 3 × 107 cm−2, whereby the dominant GR level moves closer to the mid gap position. This is supported by DLTS investigations, showing the occurrence of specific electron traps for defective epi layers, which exhibit a capture behavior that is typical for extended defects.

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“…In FinFETs, short-channel effects were notably reduced, resulting in nearly similar SS values between shortchannel and long-channel devices. 44) Most of the D-mode GaAs MOSFETs in Table I did not report the SS values, which were expected to be high because their D it values were in the range of 10 12 eV −1 cm −2 or higher. The use of ex situ oxides as gate dielectrics on (In) GaAs(100) resulted in SS values ranging from above 200 to 96 mV dec −1 , as listed in Table II.…”

Section: Resultsmentioning

confidence: 99%

GaAs MOSFETs with in situ Y₂O₃ dielectric: attainment of nearly thermally limited subthreshold slope and enhanced drain current via accumulation

Liu,

Young,

Lin

et al. 2023

Jpn. J. Appl. Phys.

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Planar GaAs(100) depletion-mode (D-mode) metal-oxide-semiconductor field-effect transistors (MOSFETs) as passivated with in-situ deposited Al2O3/Y2O3 dielectric have shown enhancement of the drain current by 167% and 333% as the gate voltage (Vg ) increased from Vg = Vfb = 0.5 V to Vg = 2 V and Vg = 4 V, where Vfb is the flat-band voltage, respectively, much higher than those in the previously published GaAs-based D-mode MOSFETs. In addition, we have achieved a high Ion/Ioff of 107 and a subthreshold slope (SS) of 63 mV/dec, which approaches the thermal limit of 60 mV/dec at 300 K and is the record-low value among planar (In)GaAs MOSFETs. Moreover, using the measured SS data, we have deduced an interfacial trap density (Dit ) of 4.1 × 1011 eV-1cm-2 from our Al2O3/Y2O3/GaAs MOSFET, the lowest among the planar (In)GaAs MOSFETs.

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InGaAs FinFETs 3-D Sequentially Integrated on FDSOI Si CMOS With Record Performance

Cited by 14 publications

References 23 publications

Systematic Modeling of Electrostatics, Transport, and Statistical Variability Effects of Interface Traps in End-of-the-Roadmap III–V MOSFETs

Systematic Modeling of Electrostatics, Transport, and Statistical Variability Effects of Interface Traps in End-of-the-Roadmap III–V MOSFETs

Electrical Activity of Extended Defects in Relaxed In_xGa_1−xAs Hetero-Epitaxial Layers

GaAs MOSFETs with in situ Y₂O₃ dielectric: attainment of nearly thermally limited subthreshold slope and enhanced drain current via accumulation

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InGaAs FinFETs 3-D Sequentially Integrated on FDSOI Si CMOS With Record Performance

Cited by 14 publications

References 23 publications

Systematic Modeling of Electrostatics, Transport, and Statistical Variability Effects of Interface Traps in End-of-the-Roadmap III–V MOSFETs

Systematic Modeling of Electrostatics, Transport, and Statistical Variability Effects of Interface Traps in End-of-the-Roadmap III–V MOSFETs

Electrical Activity of Extended Defects in Relaxed InxGa1−xAs Hetero-Epitaxial Layers

GaAs MOSFETs with in situ Y2O3 dielectric: attainment of nearly thermally limited subthreshold slope and enhanced drain current via accumulation

Contact Info

Product

Resources

About

Electrical Activity of Extended Defects in Relaxed In_xGa_1−xAs Hetero-Epitaxial Layers

GaAs MOSFETs with in situ Y₂O₃ dielectric: attainment of nearly thermally limited subthreshold slope and enhanced drain current via accumulation