High performance and low power design techniques for ASIC and custom in nanometer technologies

Chinnery, David

doi:10.1145/2451916.2451923

Cited by 7 publications

(7 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As a side effect, the delay of those fanout cells increases, thus they should not themselves lie on critical paths. We select downsizing candidates as fanout cells of critical path cells c based on the sensitivity function, SF down = C out (c)/size(c), where C out (c) is the capacitance driven by cell c. 3 If downsizing a candidate cell decreases negative slack, we restore previous size and continue to the next candidate.…”

Section: High-performance Optimizationmentioning

confidence: 99%

See 1 more Smart Citation

High-performance gate sizing with a signoff timer

Kahng

Kang

Lee

et al. 2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

View full text Add to dashboard Cite

Process and device scaling in late-CMOS technologies highlight leakage power as a critical challenge for the semiconductor industry. Careful gate sizing and V th -swapping can reduce leakage, but prior optimizations based on convex or dynamic programming (i) are often based on unrealistic assumptions about circuit delay and slew propagation, (ii) fail to handle practical design rules such as transition time or load upper bounds, and (iii) do not scale well to input complexities when full extracted parasitics are available. Seeing substantial opportunities for improvement, we present a multithreaded, stochastic optimization (Trident2.0) for gate sizing and V th assignment to minimize leakage power subject to capacitance, slew and timing constraints. Scalability and high performance of Trident2.0 are validated on ISPD-2013 Gate Sizing Contest benchmarks.

show abstract

Section: High-performance Optimizationmentioning

confidence: 99%

“…Such optimization can be difficult due to the need for accurate timing analysis on large circuit netlists. Chinnery reported 13-hour runtime when sizing 361K gates [3].…”

Section: Introductionmentioning

confidence: 99%

High-performance gate sizing with a signoff timer

Kahng

Kang

Lee

et al. 2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

View full text Add to dashboard Cite

show abstract

“…Towards this, much literature has provided various DVS schemes on different designs [1] [6] [13] [18][23] [26]. Most of them take information that can be monitored at runtime such as current performance, workload, slack, and/or temperature as inputs (states) to decide the optimal operating voltage policy, usually in the format of a state table.…”

Section: Introductionmentioning

confidence: 99%

“…Recently, several studies have shown the success on the adoption of Q-learning in circuit designs [6][27] [30]. Q-learning is a modelfree reinforcement learning technique that can be used to find an optimal action-selection policy for any given (finite) Markov decision process (MDP) [24].…”

Section: Introductionmentioning

confidence: 99%

Q-Learning Based Dynamic Voltage Scaling for Designs with Graceful Degradation

Chen

Wen

Wang

et al. 2015

Proceedings of the 2015 Symposium on International Symposium on Physical Design

View full text Add to dashboard Cite

Dynamic voltage scaling (DVS) has been widely used to suppress power consumption in modern designs. The decision of optimal operating voltage at runtime should consider the variations in workload, process as well as environment. As these variations are hard to predict accurately at design time, various reinforcement learning based DVS schemes have been proposed in the literature. However, none of them can be readily applied to designs with graceful degradation, where timing errors are allowed with bounded probability to trade for further power reduction. In this paper, we propose a Q-learning based DVS scheme dedicated to the designs with graceful degradation. We compare it with two deterministic DVS schemes, i.e., a stepping based scheme and a statistical modeling based scheme. Experimental results on three 45nm industrial designs show that the proposed Q-learning based scheme can achieve up to 83.9% and 29.1% power reduction respectively with 0.01 timing error probability bound. To the best of the authors' knowledge, this is the first in-depth work to explore reinforcement learning based DVS schemes for designs with graceful degradation.

show abstract

“…This is a natural choice in terms of power consumption because each mesh can be gated whenever the block it spans is not actively switching. Furthermore, it is well known that mesh consumes more power than standard clock tree network [5] due to more wire capacitance and excessive short-circuit current; a study indicates that 33.4 % more power is consumed in comparison with the standard clock tree [6], so it helps to gate mesh whenever it is possible. A single big mesh, however, may be inserted instead after some clock gating hierarchies are removed, which is also illustrated in Fig.…”

Section: Introductionmentioning

confidence: 99%

Design and Optimization of Multiple-Mesh Clock Network

Jung

Lee

Shin

2015

VLSI-SoC: Internet of Things Foundations

View full text Add to dashboard Cite

International audienceA clock mesh, in which clock signals are shorted at mesh grid, is less susceptible to on-chip process variation, and so it has widely been studied recently for a clock network of smaller skew. A practical design may require more than one mesh primarily because of hierarchical clock gating architecture; a single mesh, however, can also support the same architecture after some hierarchies are removed but at the cost of gating efficiency. We experimentally compare multiple- and single-mesh using a few test circuits, and show that the former consumes smaller clock power (16.3 %) but exhibits larger clock skew (10.2 ps) and longer clock wirelength (21.7 %). We continue to study how multiple meshes should be floorplanned on the layout, specifically whether or not we allow the overlaps among meshes. The choice is translated into different physical design strategy, and causes different amount of clock skew, critical path delay, clock wirelength, and clock power consumption, which we experimentally evaluate. We give at last the comparison of clock skew variation for each mesh implementation and clock tree, and show that floorplanning of multiple meshes helps to reduce the variation of clock skew

show abstract

High performance and low power design techniques for ASIC and custom in nanometer technologies

Cited by 7 publications

References 23 publications

High-performance gate sizing with a signoff timer

High-performance gate sizing with a signoff timer

Q-Learning Based Dynamic Voltage Scaling for Designs with Graceful Degradation

Design and Optimization of Multiple-Mesh Clock Network

Contact Info

Product

Resources

About