High-performance gate sizing with a signoff timer

Kahng, Andrew B.; Kang, Seokhyeong; Lee, Hyein; Markov, Igor L.; Thapar, Pankit

doi:10.1109/iccad.2013.6691156

Cited by 23 publications

(7 citation statements)

References 23 publications

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“…In addition, scalarizing methods (e.g., a popular one, weighted sum function) are proposed to decompose the complexity of multi-objective problems due to its high search efficiency [33]. However, the device physics of ICs imply nonconvexities and non-linearity [34] so that the weighted sum method is not sufficient to search for feasible Pareto-optimal solutions [33].…”

Section: Discussionmentioning

confidence: 99%

Multi-objective Optimisation of Digital Circuits based on Cell Mapping in an Industrial EDA Flow

Cao¹,

Bale²,

Trefzer

2021

Preprint

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Modern electronic design automation (EDA) tools can handle the complexity of state-of-the-art electronic systems by decomposing them into smaller blocks or cells, introducing different levels of abstraction and staged design flows. However, throughout each independent-optimised design step, overhead and inefficiency can accumulate in the resulting overall design. Performing design-specific optimisation from a more global viewpoint requires more time due to the larger search space, but has the potential to provide solutions with improved performance. In this work, a fully-automated, multi-objective (MO) EDA flow is introduced to address this issue. It specifically tunes drive strength mapping, preceding physical implementation, through multi-objective population-based search algorithms. Designs are evaluated with respect to their power, performance and area (PPA). The proposed approach is capable of expanding the design space, offering a set of Pareto-optimised trade-off solutions for different case-specific utilisation. We have applied the proposed MOEDA framework to ISCAS-85 benchmark circuits using a commercial 65nm standard cell library. The experimental results demonstrate how the MOEDA flow enhances the solutions initially generated by the standard digital flow, and how simultaneously a significant improvement in PPA metrics is achieved.

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Section: Discussionmentioning

confidence: 99%

Multi-objective Optimisation of Digital Circuits based on Cell Mapping in an Industrial EDA Flow

Cao¹,

Bale²,

Trefzer

2021

Preprint

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“…We use a Tcl-socket interface (Tcl/Tk 8.4 [23]) to communicate with P&R and timer tools similar to Trident2.0 [7] and SensOpt [24]. We have applied our proposed method to a set of open-source designs [19], which we synthesize from RTL using Synopsys Design Compiler H-2013.03-SP3 [22].…”

Section: Methodsmentioning

confidence: 99%

“…Our gate sizing method is based on sensitivity-guided gate sizing [6] [7]. In addition to timing constraints, we consider the placement constraints (P1)(P2) described in Section 3.…”

Section: Minimum Implant Area-aware Gate Sizingmentioning

confidence: 99%

Minimum implant area-aware gate sizing and placement

Kahng

Lee

2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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With reduction of minimum feature size, the minimum implant area (MinIA) constraint is emerging as a new challenge for the physical implementation flow in sub-22nm technology. In particular, the MinIA constraint induces a new problem formulation wherein gate sizing and V t -swapping must now be linked closely with detailed placement changes. To solve this new problem, we propose heuristic methods that fix MinIA violations and reduce power with gate sizing while minimizing placement perturbation to avoid creating extra timing violations. Compared to recent versions of commercial P&R tools, our methodologies achieve significant reductions (up to 100%) in the number of MinIA violations under timing/power constraints.

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“…We are grateful to the authors of the academic tools studied [6] [8] [16] [17] [20] [26] for providing binaries of their optimizers for use in our study.…”

Section: Acknowledgmentsmentioning

confidence: 99%

Horizontal benchmark extension for improved assessment of physical CAD research

Kahng

Lee

2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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The rapid growth in complexity and diversity of IC designs, design flows and methodologies has resulted in a benchmark-centric culture for evaluation of performance and scalability in physicaldesign algorithm research. Landmark papers in the literature present vertical benchmarks that can be used across multiple design flow stages; artificial benchmarks with characteristics that mimic those of real designs; artificial benchmarks with known optimal solutions; as well as benchmark suites created by major companies from internal designs and/or open-source RTL. However, to our knowledge, there has been no work on horizontal benchmark creation, i.e., the creation of benchmarks that enable maximal, comprehensive assessments across commercial and academic tools at one or more specific design stages. Typically, the creation of horizontal benchmarks is limited by mismatches in data models, netlist formats, technology files, library granularity, etc. across different tools, technologies, and benchmark suites. In this paper, we describe methodology and robust infrastructure for "horizontal benchmark extension" that permits maximal leverage of benchmark suites and technologies in "apples-to-apples" assessment of both industry and academic optimizers. We demonstrate horizontal benchmark extensions, and the assessments that are thus enabled, in two well-studied domains: place-and-route (four combinations of academic placers/routers, and two commercial P&R tools) and gate sizing (two academic sizers, and three commercial tools). We also point out several issues and precepts for horizontal benchmark enablement.

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High-performance gate sizing with a signoff timer

Cited by 23 publications

References 23 publications

Multi-objective Optimisation of Digital Circuits based on Cell Mapping in an Industrial EDA Flow

Multi-objective Optimisation of Digital Circuits based on Cell Mapping in an Industrial EDA Flow

Minimum implant area-aware gate sizing and placement

Horizontal benchmark extension for improved assessment of physical CAD research

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