Minimum implant area-aware gate sizing and placement

Abstract

With reduction of minimum feature size, the minimum implant area (MinIA) constraint is emerging as a new challenge for the physical implementation flow in sub-22nm technology. In particular, the MinIA constraint induces a new problem formulation wherein gate sizing and V t -swapping must now be linked closely with detailed placement changes. To solve this new problem, we propose heuristic methods that fix MinIA violations and reduce power with gate sizing while minimizing placement perturbation to avoid creating extra timing violations. Compared to recent versions of commercial P&R tools, our methodologies achieve significant reductions (up to 100%) in the number of MinIA violations under timing/power constraints.

New game, new goal posts

“…(This weakens or even obviates the strategy in Figure 1.) The work of [24] proposes heuristics to fix MinIA violations and reduce power with gate sizing, while minimizing placement perturbations that potentially create new timing violations. The proposed methods substantially reduce (by up to 100%) the number of MinIA violations while satisfying timing/power constraints, compared to recent versions of commercial P&R tools.…”

Lithography-induced limits to scaling of design quality

“…Kahng and Lee propose to use multiple timing models to give more flexibility at timing path boundaries, thus recovering significant "free" margins and reducing the number of timing violations that require unnecessary fixes. 23 They exploit a flexible flip-flop timing model that captures the three-way tradeoff among setup time, hold time and c2q delay (see Figure 11 (a)), so as to reduce pessimism in timing analysis of setup-or hold-critical paths. A sequential linear programming optimization for multiple corners is used to selectively analyze setup-or hold-critical paths with less pessimism.…”