High Performance and Stable Flexible Memory Thin-Film Transistors Using In–Ga–Zn–O Channel and ZnO Charge-Trap Layers on Poly(Ethylene Naphthalate) Substrate

Jang

ACS Appl. Electron. Mater.

et al. 2020

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Charge-trap memory thin-film transistors (CTM-TFTs) were fabricated with wavy-dimensional structures, and their device performances were demonstrated under mechanically stretching conditions. The fabricated CTM-TFTs obtained a wide memory window of 23.8 V, a steep subthreshold swing of 0.31 V/dec, and a large memory margin (106) with program pulses as short as 1 μs. Furthermore, the total variations in device parameters could be suppressed within a range of <12% even under stretching conditions with a prestrain as large as 60%. The mechanical durability during the cyclic stretching test with a strain of 50% was significantly improved from 2000 to 30000 cycles when the PI film thickness was reduced from 5.0 to 1.2 μm. The effects of PI thickness on the mechanical stability of the CTM-TFTs were quantitatively discussed from a viewpoint of surface strain. The difference in critical radius of curvature and the influence of the local strain induced by the spatial fluctuations of the wavy structure were suggested to be critical issues, and hence, the neutral mechanical plane was introduced for further improvement. As a result, the stretchable CTM-TFTs exhibited stable operations until 150000 stretching cycles by the contributions of an ultrathin substrate and a neutral mechanical plane.

Section: Resultsmentioning

confidence: 99%

Improvement in Mechanical Durability of Stretchable Charge-Trap Memory Transistors with Engineered Wavy-Dimensional Structures

Jang

ACS Appl. Electron. Mater.

et al. 2020

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Symp Digest of Tech Papers

“…Finally, 90nm-thick aluminum (Al) is deposited by thermal evaporation as a gate metal for both TFTs. It is patterned by a lift-off process [4][5][6]. An optical microscopy image of the fabricated multilevel memory is shown in Fig.…”

Section: Fabricationmentioning

confidence: 99%

P‐50: Development of Multilevel Memory Consisting of Oxide TFTs

Yun

Lee

et al. 2017

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This paper proposes a multilevel memory circuit with a simple structure composed of two oxide thin film transistors (Ox-TFTs) and one capacitor. The proposed memory circuit utilizes low leakage current characteristics of the Ox-TFT. Simulation and measurement results confirm that the proposed memory circuit can achieve multilevel memory feature. Author Keywordsmultilevel memory; oxide thin film transistor (Ox-TFT); low leakage current P-50 / S.-H. Yun SID 2017 DIGEST • 1427

IEEE J. Electron Devices Soc.

“…According to prior researches on the ZnO CTLs, [10] the memory device showed the V TH shift of 2.35 V when the gate voltage was swept from −25 to 25 V for P/E operations. Previously, the CTM-TFTs were successfully demonstrated to exhibit sound memory characteristics on plastic PEN substrates as well as rigid glass substrates [11]- [12]. Therefore, the oxide semiconductor, especially ZnO, is a potential CTL candidate for the oxide CTM TFTs.…”

Section: Introductionmentioning

confidence: 99%

Impacts of HfO₂/ZnO Stack-Structured Charge-Trap Layers Controlled by Atomic Layer Deposition on Nonvolatile Memory Characteristics of In-Ga-Zn-O Channel Charge-Trap Memory Thin-Film Transistors

Yoon

2019

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We fabricated the charge-trap memory thin film transistors (CTM-TFTs) using InGaZnO (IGZO) active channel and HfO 2 /ZnO stack-structured charge-trap layer (CTL). To investigate the effects of the number and thickness of HfO 2 layers inserted between the ZnO within the stack structured CTLs on the device characteristics, 2-nm-thick HfO 2 thin films were inlaid once, twice, and four times, and 4-nm-thick HfO 2 layers were introduced twice between the ZnO layers. The CTM-TFTs using the stack structured CTLs with 4-nm-thick HfO 2 layers showed good memory characteristics, including large memory window (MW) of 25 V and rapid program/erase (P/E) speed of 500 μs because of high total trap density of HfO 2 with a sufficient thickness to provide charge-trap centers. On the contrary, relatively narrow MW of 16 V and slower P/E speed of 100 ms were obtained for memory device using the stacked CTL with four HfO 2 layers of 2 nm. The HfO 2 layer with a thickness as thin as 2 nm was supposed to act as just dielectric films deactivating the trapping or migration of electron charges due to too thin film thickness. The gate-stack structures confirmed from STEM images suggested that the modulations in memory device characteristics with different CTL structures resulted from the variations in designs of stack structured CTLs when the interface qualities within the gate-stacks were well prepared. Moreover, the detailed fabrication conditions were found to be important control parameters to reproducibly obtain reliable memory device characteristics.INDEX TERMS High-k material, HfO 2 , ZnO, ALD, IGZO charge-trap memory. SO-YEONG NA was born in South Korea in 1995. She received the B.S. degree from the