High-performance architecture for dynamically updatable packet classification on FPGA

Qu, Yun R.; Zhou, Shijie; Prasanna, Viktor K.

doi:10.1109/ancs.2013.6665195

Cited by 27 publications

(28 citation statements)

References 19 publications

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“…Our construction of a modular PE is very different from prior works [15,19], where TCAM-like organizations are used and only prefix or exact match fields can be handled efficiently.…”

Section: Modular Processing Elementmentioning

confidence: 98%

“…We show an example in Figure 1: (1) each 8-bit upperbound is split into two 4-bit strides; (2) three 4-bit strides are further partitioned into 3 subsets, each corresponding to 1 upperbound. Compared to prior decomposition-based approaches [15,19] where only prefixes or exact values are divided, our approach in this paper provides a technique dividing a generic range boundary (not limited to a prefix or an exact value) into smaller chunks of strides; this also requires a new merging technique to be developed in Section 3.2.…”

Section: (Partitioning) We Partition All the Upperbounds Intomentioning

confidence: 98%

“…The FPGA-based approaches exploit efficient hardware reconfigurable architectures [15,18,19]. These approaches support high throughput for rule sets of moderate size.…”

Section: Platformsmentioning

confidence: 99%

“…For a modular PE, a straightforward organization is to record the comparison results using a Bit Vector (BV) of n bits [7,19]. For a Wm-bit field, a row of Wm s modular PEs can be connected, each comparing an s-bit input stride against n strides of n range boundaries.…”

Section: Modular Processing Elementmentioning

confidence: 99%

See 3 more Smart Citations

Optimizing many-field packet classification on FPGA, multi-core general purpose processor, and GPU

Zhang

Zhou

et al. 2015

2015 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS)

Self Cite

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Due to the rapid growth of Internet, there is an increasing need for efficiently classifying packets with many header fields in large rule sets. For example, in Software Defined Networking (SDN), the OpenFlow table lookup can require 15 packet header fields to be examined. In this paper, we present several decomposition-based packet classification implementations with efficient optimization techniques. In the searching phase, packet headers are split or combined. In the merging phase, the partial searching results from all the fields are merged to generate the final result. We prototype our implementations on state-of-the

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“…Our construction of a modular PE is very different from prior works [15,19], where TCAM-like organizations are used and only prefix or exact match fields can be handled efficiently.…”

Section: Modular Processing Elementmentioning

confidence: 98%

Section: (Partitioning) We Partition All the Upperbounds Intomentioning

confidence: 98%

“…The FPGA-based approaches exploit efficient hardware reconfigurable architectures [15,18,19]. These approaches support high throughput for rule sets of moderate size.…”

Section: Platformsmentioning

confidence: 99%

Section: Modular Processing Elementmentioning

confidence: 99%

See 2 more Smart Citations

Optimizing many-field packet classification on FPGA, multi-core general purpose processor, and GPU

Zhang

Zhou

et al. 2015

2015 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS)

Self Cite

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show abstract

“…This approach can achieve very high throughput (>1,000 MPPS); however, it suffers from memory expansion and can only support up to 1 K 5-field rules. An enhanced version based on systolic array is also proposed in [28]. A throughput of 600 MPPS can be achieved for a 1 K 15-field rule set.…”

Section: Approaches On Fpgamentioning

confidence: 99%

A Decomposition-Based Approach for Scalable Many-Field Packet Classification on Multi-core Processors

Zhou

Prasanna

2014

Int J Parallel Prog

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As a kernel function in network routers, packet classification requires the incoming packet headers to be checked against a set of predefined rules. There are two trends for packet classification: (1) to examine a large number of packet header fields, and (2) to use software-based solutions on multi-core general purpose processors and virtual machines. Although packet classification has been widely studied, most existing solutions on multi-core systems target the classic 5-field packet classification; it is not easy to scale up their performance with respect to the number of packet header fields. In this work, we present a decomposition-based packet classification approach; it supports large rule sets consisting of a large number of packet header fields. In our approach, range-tree and hashing are used to search the fields of the input packet header in parallel. The partial results from all the fields are represented in rule ID sets; they are merged efficiently to produce the final match result. We implement our approach and evaluate its performance with respect to overall throughput and processing latency for rule set size varying from 1 to 32 K. Experimental results on state-of-the-art 16-core platforms show that, an overall throughput of 48 million packets per second and a processing latency of 2,000 ns per packet can be achieved for a 32 K rule set.

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Adopting Decision Tree Based Policy Enforcement Mechanism to Protect Reconfigurable Devices

Barbareschi

Mazzeo

Miranda

2016

Smart Innovation, Systems and Technologies

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High-performance architecture for dynamically updatable packet classification on FPGA

Cited by 27 publications

References 19 publications

Optimizing many-field packet classification on FPGA, multi-core general purpose processor, and GPU

Optimizing many-field packet classification on FPGA, multi-core general purpose processor, and GPU

A Decomposition-Based Approach for Scalable Many-Field Packet Classification on Multi-core Processors

Adopting Decision Tree Based Policy Enforcement Mechanism to Protect Reconfigurable Devices

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