Physically Unclonable Functions (PUFs) are emerging cryptographic primitives used to implement lowcost device authentication and secure secret key generation. Weak PUFs (i.e., devices able to generate a single signature or to deal with a limited number of challenges) are widely discussed in literature. One of the most investigated solutions today is based on SRAMs. However, the rapid development of low-power, high-density, high-performance SoCs has pushed the embedded memories to their limits and opened the field to the development of emerging memory technologies. The Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. In this article, we propose an innovative PUF design based on STT-MRAM memory. We exploit the high variability affecting the electrical resistance of the Magnetic Tunnel Junction (MTJ) device in anti-parallel magnetization. We will demonstrate that the proposed solution is robust, unclonable, and unpredictable.CCS Concepts: r Security and privacy → Hardware-based security protocols; r Hardware → Spintronics and magnetic technologiesAdditional Key Words and Phrases: Physically unclonable functions PUFs, STT-MRAM, emerging memory technology, security ACM Reference Format: . 2016. STT-MRAM-based PUF architecture exploiting magnetic tunnel junction fabrication-induced variability.

Approximate Computing (AxC) trades off between the level of accuracy required by the user and the actual precision provided by the computing system to achieve several optimizations such as performance improvement, energy and area reduction etc. Several AxC techniques have been proposed so far in the literature. They work at different abstraction levels and propose both hardware and software implementations. The common issue of all existing approaches is the lack of a methodology to estimate the impact of a given AxC technique on the application-level accuracy. In this paper we propose a probabilistic approach to predict the relation between component-level functional approximation and application-level accuracy. Experimental results on a set of benchmark applications show that the proposed approach is able to estimate the approximation error with good accuracy and very low computation time.

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The shrinking process of CMOS technology is reaching its physical limits, thus impacting on several aspects, such as performances, power consumption and many others. Alternative solutions are under investigation in order to overcome CMOS limitations. Among them, the memristor is one of the promising technologies. Several works have been proposed so far, describing how to implement boolean logic functions employing memristors in a crossbar architecture. In this paper, we propose a tool able to automatically map any boolean function to a memristor based crossbar implementation. The proposed tool helps to perform a design space exploration to identify the best implementation w.r.t. performances and area overhead.Index terms-Memristor crossbar, Design Space Exploration, Boolean Functions. Circuit Synthesis

In the recent years, Approximate Computing (AxC) emerged as a new paradigm for energy efficient design of Integrated Circuits (ICs).AxC is based on the intuitive observation that, while performing exact computation requires a high amount of resources, allowing selective approximations or occasional relaxations of the specifications can provide significant gains in energy efficiency and area reduction. During the manufacturing process, physical defects (either random or systematic) can affect the IC and may be the cause of faults leading to observable errors. These errors (due to faults) may worsen the accuracy reduction, already introduced during the functional approximation and possibly lead it to become unacceptable. This paper aims at investigating the challenges and the opportunities related to the test of AxC ICs.