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International audienceThe research and prototyping of new memory technologies are getting a lot of attention in order to enable new (computer) architectures and provide new opportunities for today’s and future applications. Delivering high quality and reliability products was and will remain a crucial step in the introduction of new technologies. Therefore, appropriate fault modelling, test development and design for testability (DfT) is needed. This paper overviews and discusses the challenges and the emerging solutions in testing three classes of memories: 3D stacked memories, Resistive memories and Spin-Transfer-Torque Magnetic memories. Defects mechanisms, fault models, and emerging test solutions will be discussed

Physically Unclonable Functions (PUFs) are emerging cryptographic primitives used to implement lowcost device authentication and secure secret key generation. Weak PUFs (i.e., devices able to generate a single signature or to deal with a limited number of challenges) are widely discussed in literature. One of the most investigated solutions today is based on SRAMs. However, the rapid development of low-power, high-density, high-performance SoCs has pushed the embedded memories to their limits and opened the field to the development of emerging memory technologies. The Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. In this article, we propose an innovative PUF design based on STT-MRAM memory. We exploit the high variability affecting the electrical resistance of the Magnetic Tunnel Junction (MTJ) device in anti-parallel magnetization. We will demonstrate that the proposed solution is robust, unclonable, and unpredictable.CCS Concepts: r Security and privacy → Hardware-based security protocols; r Hardware → Spintronics and magnetic technologiesAdditional Key Words and Phrases: Physically unclonable functions PUFs, STT-MRAM, emerging memory technology, security ACM Reference Format: . 2016. STT-MRAM-based PUF architecture exploiting magnetic tunnel junction fabrication-induced variability.

Due to the rapid development of hand-held electronic devices, the need for high density, low power, high performance SoCs has pushed the well-established embedded memory technologies to their limits. To overcome the existing memory issues, emerging memory technologies are being developed and implemented. The focus is placed on non-volatile technologies, which should meet the high demands of tomorrow applications. The nonvolatile memory technologies being intensively researched today are the Flash memories and the emerging resistive and magnetic type random access memories. This paper presents an overview of device level operation of these nonvolatile memories, with special emphasis on the fabrication-and aging-induced reliability issues