Challenges and Solutions in Emerging Memory Testing

Vatajelu, Elena Ioana; Prinetto, P.; Taouil, Mottaqiallah; Hamdioui, Said

doi:10.1109/tetc.2017.2691263

Cited by 46 publications

(38 citation statements)

References 99 publications

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“…Faulty devices are generally encountered in analog computing systems, due to many reasons, such as fabrication process variations, spot defects, aging phenomenon, mechanical stress, heavy device testing and utilization, etc. ( Lewyn et al, 2009 ; Vatajelu E.I. et al, 2019 ; El-Sayed et al, 2020 ).…”

Section: Resultsmentioning

confidence: 99%

Neural Coding in Spiking Neural Networks: A Comparative Study for Robust Neuromorphic Systems

et al. 2021

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Various hypotheses of information representation in brain, referred to as neural codes, have been proposed to explain the information transmission between neurons. Neural coding plays an essential role in enabling the brain-inspired spiking neural networks (SNNs) to perform different tasks. To search for the best coding scheme, we performed an extensive comparative study on the impact and performance of four important neural coding schemes, namely, rate coding, time-to-first spike (TTFS) coding, phase coding, and burst coding. The comparative study was carried out using a biological 2-layer SNN trained with an unsupervised spike-timing-dependent plasticity (STDP) algorithm. Various aspects of network performance were considered, including classification accuracy, processing latency, synaptic operations (SOPs), hardware implementation, network compression efficacy, input and synaptic noise resilience, and synaptic fault tolerance. The classification tasks on Modified National Institute of Standards and Technology (MNIST) and Fashion-MNIST datasets were applied in our study. For hardware implementation, area and power consumption were estimated for these coding schemes, and the network compression efficacy was analyzed using pruning and quantization techniques. Different types of input noise and noise variations in the datasets were considered and applied. Furthermore, the robustness of each coding scheme to the non-ideality-induced synaptic noise and fault in analog neuromorphic systems was studied and compared. Our results show that TTFS coding is the best choice in achieving the highest computational performance with very low hardware implementation overhead. TTFS coding requires 4x/7.5x lower processing latency and 3.5x/6.5x fewer SOPs than rate coding during the training/inference process. Phase coding is the most resilient scheme to input noise. Burst coding offers the highest network compression efficacy and the best overall robustness to hardware non-idealities for both training and inference processes. The study presented in this paper reveals the design space created by the choice of each coding scheme, allowing designers to frame each scheme in terms of its strength and weakness given a designs’ constraints and considerations in neuromorphic systems.

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Section: Resultsmentioning

confidence: 99%

Neural Coding in Spiking Neural Networks: A Comparative Study for Robust Neuromorphic Systems

et al. 2021

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“…At this stage, both under-polishing and over-polishing of the surface can introduce defects. Specifically, under-polishing causes issues such as orange peel coupling or offset fields which affect the hysteresis curve, while over-polishing may result in dishing or residual slurry particles that are left behind [14].…”

Section: Beol Defectsmentioning

confidence: 99%

“…Finally, existing fault modeling approaches are unsystematic, and the fault model terminology is ambiguous. For instance, Chintaluri et al [11] refer to a failed transition write fault as transition fault (TF), while Vatajelu et al [14] use the term slow write fault (SWF) to describe the same faulty behavior. In addition, the term read distrub fault (RDF) is used to describe different faulty behaviors with different failure mechanisms in [11] and [15].…”

Section: Introductionmentioning

confidence: 99%

Defect and Fault Modeling Framework for STT-MRAM Testing

Rao

Taouil

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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STT-MRAM mass production is around the corner as major foundries worldwide invest heavily on its commercialization. To ensure high-quality STT-MRAM products, effective yet cost-efficient test solutions are of great importance. This paper presents a systematic device-aware defect and fault modeling framework for STT-MRAM to derive accurate fault models which reflect the physical defects appropriately, and thereafter optimal and high-quality test solutions. An overview and classification of manufacturing defects in STT-MRAMs are provided with an emphasis on those related to the fabrication of magnetic tunnel junction (MTJ) devices, i.e., the data-storing elements. Defects in MTJ devices need to be modeled by adjusting the affected technology parameters and subsequent electrical parameters to fully capture the defect impact on both the device's electrical and magnetic properties, whereas defects in interconnects can be modeled as linear resistors. In addition, a complete single-cell fault space and nomenclature are defined, and a systematic fault analysis methodology is proposed. To demonstrate the use of the proposed framework, resistive defects in interconnect and pinhole defects in MTJ devices are analyzed for a single 1T-1MTJ memory cell. Test solutions for detecting these defects are also discussed.

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“…After the FEOL phase, the lower metal layers are deposited in the BEOL phase. Lithographic issues or misalignment may cause defects here, resulting in shorts or opens in the wiring [37]. These defects again affect both the peripherals and the memory array.…”

Section: A Defect Modelingmentioning

confidence: 99%

Testing Computation-in-Memory Architectures Based on Emerging Memories

Hamdioui

Fieback

Nagarajan

et al. 2019

2019 IEEE International Test Conference (ITC)

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Today's computing architectures and device technologies are becoming incapable of meeting the increasingly stringent demands on energy and performance posed by evolving applications. Therefore, alternative novel post-CMOS computing architectures are being explored. Some of these are Computationin-Memory (CIM) architectures based on memristive devices; they integrate the processing units and the storage in the same physical location (i.e., the memory based on memristive devices). Due to their advanced manufacturing processes, use of new materials, and dual functionality, testing such chips requires specific schemes and therefore special attention. This paper describes the need for testing CIM architectures, proposes a systematic test approach, and shows the strong dependency of the test solutions on the nature of the architecture. All of these will be demonstrated using a design that is designed for computationin-memory bit-wise logical operations.

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Challenges and Solutions in Emerging Memory Testing

Cited by 46 publications

References 99 publications

Neural Coding in Spiking Neural Networks: A Comparative Study for Robust Neuromorphic Systems

Neural Coding in Spiking Neural Networks: A Comparative Study for Robust Neuromorphic Systems

Defect and Fault Modeling Framework for STT-MRAM Testing

Testing Computation-in-Memory Architectures Based on Emerging Memories

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