High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion

Abstract

In this paper, we propose a high performance asynchronous onchip bus with multiple issue and in-order/out-of-order completion for a Globally Asynchronous Locally Synchronous (GALS) design. The proposed bus implementation can be characterized with distributed and modularized control units based on a layered architecture to support multiple issue and in-order/out-of-order completion. Simulation results reveal that throughputs of asynchronous on-chip buses with multiple issue and in-order /outof-order completion increases by 31.3%/34.3%, while power consumption overhead is only 6.76%/3.98% respectively, compared to a simple asynchronous on-chip bus with only a single issue feature.