High-performance built-in self-routing for through-silicon vias

Abstract

In this reported work, a built-in self-routing scheme is developed for exploring the through-silicon via (TSV) redundancy to the extremes. A built-in self-router consists of a built-in self-tester for testing the TSVs, and a priority switching network for selecting from M TSVs to N inter-chip interconnects. A switching cell is developed to sequentially construct the priority switching network for area reduction and synthesis regularity. Although a long latency is needed for the encoding network, the best performance during inter-chip communication can be achieved due to only one switch per tier in normal operations. In a multiple fault model with no more than M 2 N defected TSVs, the repair rate can be always 100%.

Dynamic Self-Repair Architectures for Defective Through-silicon Vias

“…To reduce hardware costs, a TSV signal shifting approach, shown in Fig. 1(c) was proposed [1]. This repair architecture has one spare TSV, and the data can be shifted to one direction where a spare TSV is located.…”

“…Because a boundary scan chain is not used after manufacturing testing, selection bits can be stored in the boundary scan cells. This reroutes a defective TSV channel to a spare channel instead of performing a shift-left or shift-right operation for all TSV channels [1], [3], [7]. A multiplexer is used to choose a data line for which there is a defective TSV.…”

“…In 3D SICs, spare TSVs, such as column or row redundancies in memory, can be mainly used as a hardware redundancy technique to repair defective TSVs between stacked dies. Previous researches have focused on hardware-redundancy based TSV repair approaches [1], [3], [6]- [7], [14]. In this paper, we propose a new BIST feature to identify defective TSVs in 3D SICs and introduce costeffective dynamic TSV repair techniques.…”

“…A number of semiconductor companies have announced 3D stacked memory products [3], [8]. TSV technology shows a blueprint in the semiconductor business to overcome the technology scaling limitation and continue Moore's Law [1], [3]. These advantages are helping companies meet the increasing market demands for high-density and low-power applications such as server applications and low-power systemon-a-chip (SoC) systems used in hand-held device applications.…”

“…The three-dimensional (3D) integration technology enables systems with direct die stacking and die-to-die bonding. Through-silicon vias (TSVs), which are vertical interconnection links, provide a plurality of benefits such as high-density, high-bandwidth, and low-power operation [1]- [3]. Multiple device layers are placed together using TSV technology forming 3D stacked integrated circuits (3D SICs) [1], [2], [4]- [7].…”