High Performance by Exploiting Information Locality through Reverse Computing

Bahi, Mouad; Eisenbeis, Christine

doi:10.1109/sbac-pad.2011.10

Cited by 1 publication

(1 citation statement)

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“…This is achieved on the main kernel of the Lattice Quantum Chromo Dynamics (LQCD) simulation program where a 10.84 per cent speed-up is gained. [40] lee et.al. introduced a warp-level register compression scheme aiming to reduce GPU power consumption .…”

Section: Consumed Registersmentioning

confidence: 97%

A survey of techniques for warp scheduling in GPUs

Sandokji

Essa

Fadel

2015

2015 IEEE Seventh International Conference on Intelligent Computing and Information Systems (ICICIS)

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The heterogeneous nature of Graphics processor unit (GPU) -CPU makes it a candidate for coming exascale systems.The cores of GPGPU-which is a cost-effective computing platform-are characterized by long periods of inactive times, which results in the underutilization of the hardware resources. This is due to several factors like the limitation of on-chip memory and register files, the inefficient scheduling mechanisms, and communication bottlenecks GPU -CPU communication. In order to counteract the underutilization of recourses, certain techniques have been proposed. In this research, many architectural and system-level techniques aiming to manage and fully leverage GPU resources are surveyed, compared and evaluated. Also, the significance and challenges of warp scheduler in GPUs are thoroughly discussed. The main purpose of this paper is to provide researchers an insight into warp scheduler techniques for GPUs, as well as motivate them to present more efficient methods for enhance performance via improve thread scheduler in future GPUs.

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Section: Consumed Registersmentioning

confidence: 97%