High performance cache replacement using re-reference interval prediction (RRIP)

Jaleel, Aamer; Theobald, Kevin B.; Steely, Simon C.; Emer, Joel

doi:10.1145/1815961.1815971

Cited by 479 publications

(445 citation statements)

References 21 publications

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“…Dynamic insertion or replacement policies have been proposed where the insert position of incoming blocks dynamically changes based on the characteristics of applications, such as working set size or whether a replacement block is dynamically selected with a reuse pattern of blocks [3,4,5]. A partition mechanism based on the utilization efficiency allocated the LLC by hit monitoring of each core [2].…”

Section: Relate Workmentioning

confidence: 99%

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An adaptive cache replacement policy based on fine-grain reusability monitor

Bang

Kee

Lim

et al. 2018

IEICE Electron. Express

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This paper proposes an adaptive cache replacement policy to select a victim block based on the reuse characteristics of stored blocks by utilizing the fine-grain reusability monitor for each cache set. The evaluation result shows that the proposed mechanism can achieve a performance improvement of about 13% on average over conventional 2 MB cache and can deliver performance comparable to four times bigger cache, i.e., an 8 MB last level cache (LLC).

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Section: Relate Workmentioning

confidence: 99%

“…To overcome this shortcoming, various advanced cache management mechanisms are investigated to improve cache performance [2,3,4,5,6].…”

Section: Introductionmentioning

confidence: 99%

An adaptive cache replacement policy based on fine-grain reusability monitor

Bang

Kee

Lim

et al. 2018

IEICE Electron. Express

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“…Even though it has an important role to hide the long memory access latency in a memory system, it has been revealed in many studies that LLC becomes less efficient as capacity increases ( [1,2]). This issue in the 2D off-chip memory system will be still maintained even in the 3D-ICs based memory system.…”

Section: Introductionmentioning

confidence: 99%

Cooperative cache memory (CCM) based on the performance efficiency for 3D stacked memory system

Lim

Park

2016

IEICE Electron. Express

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Three-dimensional (3D) memory stacking technology is one of the most promising technologies providing massive memory bandwidth, and thereby provides an opportunity to overcome performance bottlenecks in memory systems. In this paper, we analyze the performance of well-known efficient memory components such as stream buffer, L2 cache, and victim cache in order to exploit the massive memory bandwidth of the 3D stacked memory system. This paper also presents a method to determine the optimal memory capacity with the best performance efficiency (a.k.a. performance improvement efficiency (PIE)) and proposes a cooperative cache memory (CCM), which prefetches adaptively according to the memory access pattern in order to exploit the massive memory bandwidth of a 3D stacked memory system. The proposed CCM with a 512 KB L2 cache and 256 KB stream buffer with the proposed prefetching mechanism can deliver superior performance by about 13% over a conventional 8 MB L2 cache.

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“…Upon re-reference to the block, the LRU policy updates its prediction and again anticipates that the block has a near-immediate re-reference interval. In effect, the LRU replacement policy predicts that cache lines are re-referenced in reverse order of reference, i.e., the LRU policy predicts that a most recently used cache line will be re-referenced much sooner than less recently used cache lines [28].…”

Section: Introductionmentioning

confidence: 99%

“…According to prior research, there are four common kinds [28] of cache access patterns in applications: recency-friendly access patterns (for any k) ða 1 ; a 2 ; . .…”

Section: Introductionmentioning

confidence: 99%