High-performance CMOS-compatible self-aligned In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFETs with GMSAT over 2200 &#x00B5;S/&#x00B5;m at V<inf>DD</inf> = 0.5 V

Abstract

We demonstratehigh-performance self-aligned In 0.53 Ga 0.47 As-channel MOSFETs with effective channel length L EFF down to 20 nm, peak transconductance G MSAT over 2200 μS/μm at L EFF = 30 nm and supply voltage V DD = 0.5 V, thin inversion oxide thickness T INV = 1.8 nm, and low series resistance R EXT = 270 Ω.μm. These MOSFETs operate within 20% of the ballistic limit for L EFF ≤ 30 nm and are among the best In 0.53 Ga 0.47 As FETs in literature. We investigate the effects of channel/barrier doping on FET performance and show that increase in mobility beyond ~ 500 cm 2 /Vs has progressively smaller impact as L EFF is scaled down. Our self-aligned MOSFETs were fabricated using a CMOS-compatible process flow that includes gate and spacer formation using RIE, source/drain extension (SDE) implantation, and in-situ-doped raised source/drain (RSD) epitaxy. This process flow is manufacturable and easily extendable to non-planar architectures. I. INTRODUCTIONMany III-V materials have significantly better electron transport properties than Si, and therefore, have been actively investigated as the NFET solution for high-performance CMOS applications [1]. While most III-V research has been focused on HEMTs [2]-[18] or MOS-HEMTs [19]-[32], very few works have focused on MOSFETs [33]-[39]. MOSFETs are required for high performance and device density scaling because MOS-HEMTs have high overlap capacitance while HEMTs have large foot-print and high gate leakage [36]. Therefore, we have focused on self-aligned MOSFETs and processes that are not only manufacturable but also compatible with CMOS applications [36]. In this work, we demonstrate high-performance self-aligned In 0.53 Ga 0.47 As MOSFETs with L EFF down to 20 nm and peak G MSAT over 2200 μS/μm at V DD = 0.5 V. This work presents 2× higher performance compared to [36], and our devices are among the best In 0.53 Ga 0.47 As FETs in literature.

A review of InP/InAlAs/InGaAs based transistors for high frequency applications

“…Threshold voltage and Subthreshold swing Vs Gate length characteristics of enhancement mode In 0.7 Ga 0.3 As buried channel MOSFETs are shown in Fig. 4 [167,80]. Yannin Sun et al have been demonstrated the short channel behavior of E-mode In 0.70 Ga 0.30 As buried -channel MOSFETs.…”

“…The threshold voltage and DIBL Vs Gate length characteristics of enhancement mode In 0.7 Ga 0.3 As buried channel MOSFET is shown in Fig. 5 [167,80]. It has been shown that the subthreshold swing and drain induced barrier lowering increases with reduction in gate length and I on /I off also decreases with decreasing Lg which indicates severe short-channel effects for low gate length devices.…”

“…Although the InGaAs MOSFETs [167,168] do not show as good short-channel effect as InAs HEMT [169] with t ins = 4 nm due to larger EOT, the InGaAs MOSFET design should ultimately have better scalability as the top barrier and oxide layer thickness are reduced [167]. InGaAs channel MOSFETs have recently emerged as the most promising non-Si n-channel device for next generation nano scale CMOS.…”

“…The threshold voltage and DIBL Vs gate length characteristics of enhancement mode In 0.7 Ga 0.3 As buried channel MOSFET[167,80,79].…”

Monolithic III–V on Silicon Plasmonic Nanolaser Structure for Optical Interconnects

“…For instance the process can be simplified and allows for more design flexibility, much lower packaging cost, and most importantly, smaller parasitic device capacitance. Moreover, synergies can be explored between such nanoscale photonic elements and their electronic counterparts, as metal-oxide-semiconductor field-effect transistors that use III–V semiconductors as channel materials are being monolithically integrated on Si as next generation logic devices3.…”