High performance CMOS current comparator

Tang, Aoxiang; Toumazou, C.

doi:10.1049/el:19940003

Cited by 98 publications

(46 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Various architectures have since been proposed to improvise upon Traff"s structure. One such improvisation is the structure proposed by Tang [19]. Fig.…”

Section: Current Comparatormentioning

confidence: 99%

A Multi-bit High Speed Current Mode Analog to Digital Conversion Algorithm

Bhatia¹

2013

IOSR-JVSP

View full text Add to dashboard Cite

“…Various architectures have since been proposed to improvise upon Traff"s structure. One such improvisation is the structure proposed by Tang [19]. Fig.…”

Section: Current Comparatormentioning

confidence: 99%

A Multi-bit High Speed Current Mode Analog to Digital Conversion Algorithm

Bhatia¹

2013

IOSR-JVSP

View full text Add to dashboard Cite

“…These methods can be categorized into two major types according to the number of input nodes of comparator. One type of current comparator has single-input node assuming the input current is the processed subtraction between two signals [1,2,3]. The function of these comparators is incomplete because the required processed subtraction is pre-performed by other circuit.…”

Section: Introductionmentioning

confidence: 99%

Balanced low input impedances CMOS current comparator

Lin

2012

IEICE Electron. Express

View full text Add to dashboard Cite

This paper presents a continuous-time current comparator with low input impedance enhancing the accuracy of comparison. The proposed circuit employs low impedance common-gate structures as input stages and further uses common-source feedback structures to enable extremely reduction of input impedances. The input impedances are well designed to be balanced, so that the proposed design can be applied to perform precise comparison between two terminals with tiny varied currents. An implemented chip was fabricated by TSMC 0.35 µm CMOS process with its input impedances and propagation delay are 66.8 Ω, 66.6 Ω and 2.5 ns respectively while the average power consumption is about 1.64 mW.

show abstract

“…As these structures accept the difference of input currents, an additional current subtraction circuit is required for complete comparison, which will cause the variation in the reported performance parameters. (Traff, 1992;Banks et al, 2008;Chen et al, 2001;Tang & Toumazou, 1994;Min & Kim, 1998;Ravezzi et al, 1997;Tang & Pun, 2009;. In this paper, a current comparator is proposed that has an inbuilt current differencing circuitry.…”

mentioning

confidence: 99%

“…A remedy to these limitations was reported by Traff, (1992), where nonlinear feedback is introduced along with capacitive sensing, which lowers the input impedance and provides better speed. Subsequently, many structures based on concept of Traff, (1992) have been reported in various researches, (Banks et al, 2008;Chen et al, 2001;Tang et al, 1994;Min et al, 1998;Ravezzi et al, 1997;Tang et al, 2009; as an improvement over it. The comparators reported in are also based on capacitive sensing, but employ active elements, such as a current conveyor, second generation (CCII) ) and a differential current conveyor, second generation (DCCII) as reported by .…”

mentioning

confidence: 99%

“…The Design of a High Speed Nonlinear Feedback-based Current Comparator in literature which can broadly be classified on the basis of current sensing mechanism (Toumazou et al, 1990;Freitas & Current, 1993;Traff, 1992;Banks & Toumazou, 2008;Chen et al, 2001;Tang & Toumazou, 1994;Min & Kim, 1998;Ravezzi et al, 1997;Tang & Pun, 2009;. The first generation current comparators are based on sensing input current at a low impedance node followed by a voltage amplification mechanism (Frietas et al, 1993).…”

mentioning

confidence: 99%

See 1 more Smart Citation

The Design of a High Speed Nonlinear Feedback-based Current Comparator

Bhatia¹,

Pandey²,

Shridhar³

et al. 2016

IJTech

View full text Add to dashboard Cite

In this paper a new current comparator architecture is presented, which utilizes the concept of nonlinear feedback to speed up the operation. The analytical formulation for quantifying the effect of the feedback is put forward. The functionality of the proposed comparator is verified using simulations carried out on an Orcad Pspice tool using Taiwan Semiconductors Manufacturing Company (TSMC) 0.18 µm technology parameters. The resolution and delay are found to be ± 10 nA and 1.48 ns, respectively at a reference current of 1µA. The effects of parameter variations on the performance of the proposed comparator at different design corners is also studied. The usefulness of the proposed comparator is demonstrated through a 3-bit current mode flash Analog to Digital Converter (ADC) and its performance parameters are also calculated using simulations. The simulation results show that the 3-bit current mode flash Analog to Digital Converter exhibits no missing codes and has Differential Non-Linearity (DNL) of -0.25 Least Significant Bit (LSB) and Integral Non-Linearity (INL) of -0.19 LSB.

show abstract

High performance CMOS current comparator

Cited by 98 publications

References 2 publications

A Multi-bit High Speed Current Mode Analog to Digital Conversion Algorithm

A Multi-bit High Speed Current Mode Analog to Digital Conversion Algorithm

Balanced low input impedances CMOS current comparator

The Design of a High Speed Nonlinear Feedback-based Current Comparator

Contact Info

Product

Resources

About