High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs

Takato, H.; Sunouchi, K.; Okabe, N.; Nitayama, A.; Hieda, K.; Horiguchi, F.; Masuoka, F.

doi:10.1109/iedm.1988.32796

Cited by 82 publications

(22 citation statements)

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“…[1][2][3][4][5][6][7] The future may see the use of threedimensional (3D) MOSFETs, such as vertically stacked SiNW FETs, [8][9][10][11][12] for high device densities. An asymmetric channel structure is expected for the vertically stacked SiNW FETs because of the fabrication processes.…”

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confidence: 99%

Electrical characteristics of asymmetrical silicon nanowire field-effect transistors

Sato

Kakushima

Ohmori

et al. 2011

Applied Physics Letters

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This letter reports the electrical characteristics of nonuniform silicon nanowire nFETs with asymmetric source and drain widths. For electrostatic properties, reduced drain-induced barrier lowering (DIBL) is achieved in a device in which the source is wider than the drain. For carrier transport properties, higher values of surface-roughness-limited mobility (l SR ) are obtained in the sample with the wider drain size. Our electrostatic model shows that the concentration of lines of electric force is relaxed near the wider source edge, which results in smaller DIBL. The asymmetric l SR is attributed to the channel surface morphology with (110)-and (100)-faceted surfaces.

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confidence: 99%

Electrical characteristics of asymmetrical silicon nanowire field-effect transistors

Sato

Kakushima

Ohmori

et al. 2011

Applied Physics Letters

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“…1) is similar in structure to the surrounding-gate transistors (SGTs) that have been studied for more than a decade as high-density alternatives to planar transistors [4][5][6][7]. The RG-FET is novel because of the nature of its fabrication and placement within a self-assembling device structure.…”

Section: Introductionmentioning

confidence: 94%

Performance simulation of nanoscale silicon rod field-effect transistor logic

Dwyer

Vicci

Taylor

2003

IEEE Trans. Nanotechnology

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“…The first type of concepts defines source and drain by ion implantation. Such a device is especially attractive as the cell transistor in a memory, because the channel can be made long for good offcharacteristics without consuming too much area [1,2]. The next type of concepts utilizes epitaxial layers of doped silicon, which allows the fabrication of vertical short channel transistors by precisely controlling the layer thickness [3].…”

Section: Introductionmentioning

confidence: 99%

Short Channel Vertical Sidewall Transistors

Schulz

Rosner²,

Risch³

et al. 2000

30th European Solid-State Device Research Conference

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For the first time vertical n-channel MOSFETs with implanted S/D-regions and channel lengths down to 50 nm are presented, fabricated in a standard production line with iline lithography.These 50 nm transistors exhibit an excellent transconductance of 560 µS/µm, but suffer from short channel effects in the subthreshold region. The devices with 100 nm channel length, having a somewhat reduced transconductance of 445 µS/µm, showed a very low off-current of 5 pA/µm.We thereby demonstrate the possibility of integrating a high performance short channel transistor in a conventional CMOS process.

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High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs

Cited by 82 publications

References 0 publications

Electrical characteristics of asymmetrical silicon nanowire field-effect transistors

Electrical characteristics of asymmetrical silicon nanowire field-effect transistors

Performance simulation of nanoscale silicon rod field-effect transistor logic

Short Channel Vertical Sidewall Transistors

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