High performance combinatorial algorithm design on the Cell Broadband Engine processor

Bader, David A.; Agarwal, Virat; Madduri, Kamesh; Kang, Seunghwa

doi:10.1016/j.parco.2007.09.005

Cited by 25 publications

(16 citation statements)

References 22 publications

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“…Also, the simulation of the benchmarks should finish within reasonable time and the performance statistics should have a significant number of branch miss stall cycles in order to have some room for improvement. In our opinion, the selected benchmarks are a good representation of applications suitable for the Cell processor and comply with our requirements MiniGZip is a parallel SPU implementation of the GZIP (de)compression program based on the ZLIB library, implemented by Seunghwa Kang [6]. The list ranking problem is a fundamental problem for many combinatorial and graphtheoretic applications.…”

Section: Methodsmentioning

confidence: 99%

Extending the Cell SPE with Energy Efficient Branch Prediction

Briejer

Meenderinck

Juurlink

2010

Euro-Par 2010 - Parallel Processing

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Abstract. Energy-efficient dynamic branch predictors are proposed for the Cell SPE, which normally depends on compiler-inserted hint instructions to predict branches. All designed schemes use a Branch Target Buffer (BTB) to store the branch target address and the prediction, which is computed using a bimodal counter. One prediction scheme predecodes instructions when they are fetched from the local store and accesses the BTB only for branch instructions, thereby saving power compared to conventional dynamic predictors that access the BTB for every instruction. In addition, several ways to leverage the existing hint instructions for the dynamic branch predictor are studied. We also introduce branch warning instructions which initiate branch prediction before the actual branch instruction is fetched. They allow fetching the instructions starting at the branch target and thus completely remove the branch penalty for correctly predicted branches. For a 256-entry BTB, a speedup of up to 18.8% is achieved. The power consumption of the branch prediction schemes is estimated at 1% or less of the total power dissipation of the SPE and the average energy-delay product is reduced by up to 6.2%.

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Section: Methodsmentioning

confidence: 99%

Extending the Cell SPE with Energy Efficient Branch Prediction

Briejer

Meenderinck

Juurlink

2010

Euro-Par 2010 - Parallel Processing

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“…Another example is Cell Broadband Engine (Cell BE) in PlayStation3 and QS22 blade [14]. It is a heterogeneous multicore chip consisting of a traditional microprocessor called power processing element (PPE) that controls eight singleinstruction multiple-data (SIMD) co-processing units called synergistic processing elements (SPEs) [15].…”

Section: V(r) ← F({v(r′)|r′ ∈ Neighbor(r)})mentioning

confidence: 99%

High-order stencil computations on multicore clusters

Liu

Seymour

Nomura

et al. 2009

2009 IEEE International Symposium on Parallel &Amp; Distributed Processing

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“…T B is employed in the triplet because of the significant overhead due to branch misprediction in SPEs. However, since T B can be decreased by unrolling loops and inserting branch hints, it is difficult to report accurate number of actual branches [13]. When the misprediction probability is low, T B has little influence on execution time.…”

Section: (P P E) Cmentioning

confidence: 99%

“…Similar to the complexity model proposed in [13], the adapted model ignores several features of the Cell for the sake of simplifying the analysis. For example, we ignore the effect of floating point precision on the performance of numerical algorithms.…”

Section: (P P E) Cmentioning

confidence: 99%

Parallel exact inference on the Cell Broadband Engine processor

Xia¹,

Prasanna²

2008

2008 SC - International Conference for High Performance Computing, Networking, Storage and Analysis

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We present the design and implementation of a parallel exact inference algorithm on the Cell Broadband Engine (Cell BE) processor, a heterogeneous multicore architecture. Exact inference is a key problem in exploring probabilistic graphical models, where the computation complexity increases dramatically with the network structure and clique size. In this paper, we exploit parallelism in exact inference at multiple levels. We propose a rerooting method to minimize the critical path for exact inference, and an efficient scheduler to dynamically allocate SPEs. In addition, we explore potential table representation and layout to optimize DMA transfer between local store and main memory.We implemented the proposed method and conducted experiments on the Cell BE processor in the IBM QS20 Blade. We achieved speedup up to 10× on the Cell, compared to state-of-the-art processors. The methodology proposed in this paper can be used for online scheduling of directed acyclic graph (DAG) structured computations.

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High performance combinatorial algorithm design on the Cell Broadband Engine processor

Cited by 25 publications

References 22 publications

Extending the Cell SPE with Energy Efficient Branch Prediction

Extending the Cell SPE with Energy Efficient Branch Prediction

High-order stencil computations on multicore clusters

Parallel exact inference on the Cell Broadband Engine processor

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